Mixed Language Failing

[yrrapt]

I have successfully ran the VHDL and verilog examples but I am now looking at mixing languages.

I modified the pwm.vhd file to instantiate a simple inverter written in verilog. I can Verilate the inverter.v and pwm.vhd files fine but when I include the pwm_top.vhd file the process fails with the following message:

** Fatal: tree kind T_COMPONENT does not have item I_DECLS
[0x55b5f9d61021] ../src/object.c:58 object_lookup_failed
[0x55b5f9d2da17] ../src/tree.c:636 tree_decls
[0x55b5f9d5b83c] ../src/json.c:988 dump_decls
[0x55b5f9d5acd7] ../src/json.c:574 dump_decl
[0x55b5f9d5b864] ../src/json.c:990 dump_decls
[0x55b5f9d5ca34] ../src/json.c:1003 trees_to_json
[0x55b5f9d5cca4] ../src/json.c:1106 dump_json
[0x55b5f9d115d0] ../src/nvc.c:181 process_command
[0x55b5f9d0fd16] ../src/nvc.c:1061 main
%Error: nvc failed to parse one of your input files

Do you have any pointers on where I might be going wrong?

It would be super useful to be able to do mixed VHDL and verilog simulation so I am excited to see this project.

Thanks in advance for any help you could provide.

[svancau]

Hello, Thanks for the report That's the main goal of my project, having a Libre mixed language simulator ;). It is supposed to work but untested.

NVC fails somewhere with the language parsing but it's difficult to say without seeing the actual code. Can you provide me the source and command line you used so I can reproduce the issue ?

[yrrapt]

Hi,

Thanks for your response.

A mixed language simulator is a key missing component from the open source eco-system so this is exciting. Hopefully I can lend a hand, even if it's just testing and documentation.

I tried with two different mixed language hierarchies (highest level of hierarchy on the left):

VHDL -> VHDL -> verilog

and

verilog -> VHDL -> verilog

I have been using the command taken out of the Makefile (for each hierarchy):

verilator  -cc --exe -O2 -x-assign 0 --trace --trace-fst inverter.v pwm.vhd pwm_top.vhd pwm.cpp
verilator  -cc --exe -O2 -x-assign 0 --trace --trace-fst inverter.v pwm.vhd pwm_top.v pwm.cpp

Interestingly if I only Verilate the bottom two layers with:

verilator  -cc --exe -O2 -x-assign 0 --trace --trace-fst inverter.v pwm.vhd --top-module PWM

I don't get any errors, it's when I add the pwm_top.v(hd) that the parsing errors occur.

Thanks for any help you could provide.

Files used:

inverter.v

module inverter(
    input   A,
    output  Q
    );

    assign Q = !A;

endmodule

pwm.v

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm is
    generic (size : integer := 12);
    port (
        clk : in std_logic;
        duty : in unsigned(size-1 downto 0);
        out_sig : out std_logic
    );
end entity pwm;

architecture rtl of pwm is
    signal counter : unsigned(size-1 downto 0) := (others => '0');
    signal pwm_signal : std_logic;

    component inverter is
        port(
            A   :   in  std_logic;
            Q   :   out std_logic
        );
    end component inverter;

begin

    INV : inverter
        port map(
            A => pwm_signal,
            Q => out_sig
        );

end architecture rtl;

pwm_top.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm_top is
    port (
        clk : in std_logic;
        duty : in unsigned(15 downto 0);
        out_sig : out std_logic_vector(2 downto 0)
    );
end entity pwm_top;

architecture rtl of pwm_top is
    constant pwm_size : integer := 12;

begin

pwm0 : entity work.pwm
generic map(
    size => 8)
port map(
    clk => clk,
    duty => duty(7 downto 0),
    out_sig => out_sig(0));

end architecture rtl;

pwm_top.v

module pwm_top (
    input           clk,
    input [15:0]    duty,
    output [2:0]    out
);

    pwm pwm (
        .clk(clk),
        .duty(duty),
        .out_sig(out_sig)
    );

endmodule

pwm.cpp Unmodified from the file in examples/pwm

[fredrequin]

Hi there, I have used a slightly different approach with NVC : instead of generating some XML output, the tool generates a SystemVerilog output. This solution has many advantages:

• No need to create an XML parser in Verilator
• Correctness of the SystemVerilog output is easily checked with Verilator LINT tool
• SystemVerilog support in Verilator is quite good and is getting better and better
• VHDL and SystemVerilog have similar features so conversion is not that hard.

Nevertheless, Sebastien's work was very inspiring for me and I would not have done that without his various attempts of supporting VHDL in Verilator. Maybe we should join our efforts to finish the SystemVerilog support ? My NVC repo is here : https://github.com/fredrequin/nvc Best Regards, Frédéric Requin