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svofski / vector06cc

Вектор-06ц в ПЛИС / Vector-06c in FPGA
http://svofski.github.io/vector06cc/
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T80 timing: XTHL ($E3) #23

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
T80 has it strictly Z80 way: (4,3,4,3,5)
8080 must have:  (4,3,3,3,5)

Original issue reported on code.google.com by svof...@gmail.com on 21 Jan 2008 at 12:34

GoogleCodeExporter commented 9 years ago 
More:
Jcond: 5,3,3
CALL:  5,3,3,3,3
Ccond: 5,3,3,(3,3)
SPHL:  5
IN/OU: 4,3,3
INR/DCR M: 4,3,3
DAD rp: 4,3,3

Original comment by svof...@gmail.com on 21 Jan 2008 at 8:39

GoogleCodeExporter commented 9 years ago 
Hmm.. everywhere it says that JMP and Jcnd always take 10 cycles in total thus 
4+3+3

Original comment by svof...@gmail.com on 21 Jan 2008 at 9:34

GoogleCodeExporter commented 9 years ago 
Also RET: 4,3,3
     Rcond: 5 (3,3)

Original comment by svof...@gmail.com on 22 Jan 2008 at 2:55

GoogleCodeExporter commented 9 years ago 
Reviewed and fixed all but HLT. CPU test passes ok, but I don't know how to 
perform a
complete verification without wasting too much time.

HLT is different in Z80 and 8080. In 8080, after 4 TStates in M1, the CPU 
enters M2,
executes T1, T2 and enters Twh until reset or interrupted. Z80 just starts 
executing
NOP's, which probably means different interrupt reaction times. But this should 
be
verified in T80 since it's not really a real Z80.

Original comment by svof...@gmail.com on 23 Jan 2008 at 2:56