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svstuff / systemverilog

SystemVerilog stuff and stuff.
http://svstuff.github.io/systemverilog
MIT License
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vardecl with implicit type and initializer #7

Open svstuff opened 9 years ago

svstuff commented 9 years ago

Vardecl with implicit type and initializer is difficult to separate from an assignment statement. The LRM grammar is ambiguous and would require some semantic predicate magic to disambiguate.

Rather than doing that I've just relaxed the grammar to allow interleaving declarations and statements and made certain variable declarations (of the form "a = b;") be treated as an assignment statement.

I'm sure this could be handled in the grammar if my antlr-fu was better, but for now it seems easier to handle this in the semantic phase.

svstuff commented 9 years ago

Leaving this open because this relaxation needs to be followed up with a semantic check.