Some questions about using the create_project tcl command to generate a project.

[siyue0208]

Dear author,

Thank you very much for your contribution to the FPGAlink project using Timetagger. As a scholar using this project for the first time, I still have some questions.

1. In the create_project tcl command, "[file normalize "$origin_dir/gen_srcs/eth_crc_128b_comb.v"]" confuses me because I couldn't find the gen_srcs folder and eth_crc_128b_comb.v file in the entire directory.

2. Since I haven't ordered any products from FrontPanel company, I am unable to download the FrontPanel SDK as it requires an order number for verification. But we already have relevant purchasing plans. So, can the .v files related to the FrontPanel SDK in the create_project tcl be safely removed without affecting the project?

I would greatly appreciate any related responses. Thank you!

[david-sawatzke]

Hello siyue,

In the create_project tcl command, "[file normalize "$origin_dir/gen_srcs/eth_crc_128b_comb.v"]" confuses me because I couldn't find the gen_srcs folder and eth_crc_128b_comb.v file in the entire directory.

These sources are generated by the Makefile in the root directory, the Getting Started section might help you. Python 3 is required.

Since I haven't ordered any products from FrontPanel company, I am unable to download the FrontPanel SDK as it requires an order number for verification. But we already have relevant purchasing plans. So, can the .v files related to the FrontPanel SDK in the create_project tcl be safely removed without affecting the project?

Sorry, this is unfortunately not easily doable. The OpalKelly FrontPanel interface is used for interacting with the internal Wishbone bus and also provides the clock it, thus the USB-Wishbone interface and associated signals would need to be removed/replaced to build the project without the FrontPanel SDK.

If you have any more questions, might also want to contact our support team directly at support@swabianinstruments.com .

Greetings

David