6k display unable to utilize full resolution

[supermarin]

• Sway Version:

  • 1.9

• Debug Log: TBD - will attach

Opening a dedicated issue for this comment. After the drm changes between 1.8.1 and 1.9, I can't drive Apple XDR display at full resolution anymore. Installed 1.8.1 today to double confirm this and can 100% reproduce. Here's how swaymsg -t get_outputs looks like in 1.8.1:

Output DP-2 'Apple Computer Inc ProDisplayXDR 0x00001F08' (focused)
  Current mode: 6016x3384 @ 60.000 Hz
  Position: 1920,0
  Scale factor: 2.000000
  Scale filter: nearest
  Subpixel hinting: unknown
  Transform: normal
  Workspace: 3
  Max render time: off
  Adaptive sync: disabled
  Available modes:
    6016x3384 @ 60.000 Hz
    3840x2160 @ 60.000 Hz
    6016x3384 @ 59.940 Hz
    6016x3384 @ 50.000 Hz
    6016x3384 @ 48.000 Hz
    6016x3384 @ 47.952 Hz
    5120x2880 @ 60.000 Hz
    5120x2880 @ 59.940 Hz
    5120x2880 @ 50.000 Hz
    5120x2880 @ 48.000 Hz
    5120x2880 @ 47.952 Hz
    3840x2160 @ 60.000 Hz
    3840x2160 @ 59.939 Hz
    3840x2160 @ 50.000 Hz
    3840x2160 @ 47.952 Hz
    3840x2160 @ 47.999 Hz
    2560x2880 @ 59.999 Hz
    2560x2880 @ 59.939 Hz
    2560x2880 @ 50.000 Hz
    2560x2880 @ 48.000 Hz
    2560x2880 @ 47.951 Hz
    2560x1440 @ 59.999 Hz

Output DP-3 'Apple Computer Inc ProDisplayXDR 0x00001F08' (inactive)
  Available modes:
    2560x2880 @ 59.999 Hz
    2560x2880 @ 59.939 Hz
    2560x2880 @ 50.000 Hz
    2560x2880 @ 48.000 Hz
    2560x2880 @ 47.951 Hz

Note it shows two DP- outputs for the same monitor (DP-2 and DP-3), and the screen can operate in 6016x3384@60hz scale 2.

With 1.9, I'm seeing only 1 DP-2 output but the screen tops out at 4k and everything looks blurry. Manually setting resolution via swaymsg output DP-2 mode 6016x3384@60hz scale 2 does nothing and produces a line in sway log saying it can't commit the output (will capture the exact line when I run 1.9 again).

[supermarin]

Launched sway 1.9 with sway -d 2>/tmp/sway.log, and this is the output if I try to do swaymsg output DP-1 mode 6016x3384@60Hz scale 2:

00:04:13.625 [DEBUG] [sway/ipc-server.c:197] New client: fd 80
00:04:13.625 [INFO] [sway/commands.c:261] Handling command 'output DP-1 mode 6016x3384@60Hz scale 2'
00:04:13.625 [DEBUG] [sway/commands.c:436] Subcommand: mode 6016x3384@60Hz scale 2
00:04:13.625 [DEBUG] [sway/commands.c:436] Subcommand: scale 2
00:04:13.625 [DEBUG] [sway/config/output.c:212] Merging on top of existing output config
00:04:13.625 [DEBUG] [sway/config/output.c:235] Config stored for output DP-1 (enabled: -1) (6016x3384@60.000000Hz position -1,-1 scale 2.000000 subpixel unknown transform -1) (bg #182d2a solid_color) (power -1) (max render time: -1)
00:04:13.625 [DEBUG] [sway/config/output.c:401] Turning on output DP-1
00:04:13.625 [DEBUG] [sway/config/output.c:409] Set DP-1 mode to 6016x3384 (60.000000 Hz)
00:04:13.625 [INFO] [sway/config/output.c:277] Assigning configured mode (6016x3384@60.000Hz) to DP-1
00:04:13.625 [DEBUG] [sway/config/output.c:448] Auto-detected output transform: 0
00:04:13.625 [DEBUG] [sway/config/output.c:476] Set DP-1 scale to 2.000000
00:04:13.625 [DEBUG] [sway/config/output.c:520] Committing output DP-1
00:04:13.625 [DEBUG] [wlr] [types/output/render.c:168] Attaching empty buffer to output for modeset
00:04:13.625 [DEBUG] [wlr] [types/output/swapchain.c:27] Choosing primary buffer format XR24 (0x34325258) for output 'DP-1'
00:04:13.625 [DEBUG] [wlr] [types/output/swapchain.c:96] Testing swapchain for output 'DP-1'
00:04:13.625 [DEBUG] [wlr] [render/swapchain.c:106] Allocating new swapchain buffer
00:04:13.632 [DEBUG] [wlr] [render/allocator/gbm.c:145] Allocated 6016x3384 GBM buffer with format XR24 (0x34325258), modifier Y_TILED_GEN12_RC_CCS_CC (0x0100000000000008)
00:04:13.632 [DEBUG] [wlr] [backend/drm/atomic.c:73] connector DP-1: Atomic commit failed: Invalid argument
00:04:13.632 [DEBUG] [wlr] [backend/drm/atomic.c:77] (Atomic commit flags: ATOMIC_TEST_ONLY | ATOMIC_ALLOW_MODESET)
00:04:13.632 [DEBUG] [wlr] [types/output/swapchain.c:98] Output test failed on 'DP-1', retrying without modifiers
00:04:13.632 [DEBUG] [wlr] [types/output/swapchain.c:27] Choosing primary buffer format XR24 (0x34325258) for output 'DP-1'
00:04:13.632 [DEBUG] [wlr] [types/output/swapchain.c:107] Testing modifier-less swapchain for output 'DP-1'
00:04:13.632 [DEBUG] [wlr] [render/swapchain.c:106] Allocating new swapchain buffer
00:04:13.638 [DEBUG] [wlr] [render/allocator/gbm.c:145] Allocated 6016x3384 GBM buffer with format XR24 (0x34325258), modifier INVALID (0x00FFFFFFFFFFFFFF)
00:04:13.638 [DEBUG] [wlr] [backend/drm/atomic.c:73] connector DP-1: Atomic commit failed: Invalid argument
00:04:13.638 [DEBUG] [wlr] [backend/drm/atomic.c:77] (Atomic commit flags: ATOMIC_TEST_ONLY | ATOMIC_ALLOW_MODESET)
00:04:13.638 [ERROR] [wlr] [types/output/swapchain.c:109] Swapchain for output 'DP-1' failed test
00:04:13.638 [ERROR] [sway/config/output.c:525] Failed to commit output DP-1
00:04:13.638 [INFO] [sway/ipc-server.c:571] IPC Client 80 disconnected
00:04:14.939 [DEBUG] [sway/ipc-server.c:327] Sending window::focus event
00:04:14.939 [DEBUG] [sway/tree/arrange.c:263] Usable area for ws: 3840x2136@0,24
00:04:14.939 [DEBUG] [sway/tree/arrange.c:297] Arranging workspace '3' at 1927.000000, 31.000000
00:04:14.939 [DEBUG] [sway/tree/arrange.c:77] Arranging 0x7ffc94a83420 horizontally
00:04:14.939 [DEBUG] [sway/tree/arrange.c:156] Arranging 0x7ffc94a83340 vertically
00:04:14.939 [DEBUG] [sway/tree/arrange.c:156] Arranging 0x7ffc94a83340 vertically
00:04:14.939 [DEBUG] [sway/desktop/transaction.c:398] Transaction 0x227ca10 committing with 6 instructions
00:04:14.939 [DEBUG] [sway/desktop/transaction.c:294] Applying transaction 0x227ca10

[emersion]

Can you obtain DRM debug logs? See https://github.com/swaywm/wlroots/wiki/DRM-Debugging

[supermarin]

Yep, here you go: dmesg.log sway.log

[emersion]

Hm, not sure what's up here… Maybe an issue with the "max bpc" property?

[96745.396348] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:246:DP-1] Limiting display bpp to 24 (EDID bpp 30, max requested bpp 24, max platform bpp 36)
[96745.396429] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] Try DSC (fallback=no, joiner=yes, force=no)
[96745.396474] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:245:DDI TC3/PHY D][CRTC:80:pipe A] DP link limits: pixel clock 1286010 kHz DSC on max lanes 4 max rate 810000 max pipe_bpp 24 max link_bpp 24.0000
[96745.396520] i915 0000:00:02.0: [drm:intel_dp_dsc_compute_config [i915]] No Valid pipe bpp for given mode ret = -22
[96745.396570] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] Try DSC (fallback=no, joiner=yes, force=no)
[96745.396613] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:245:DDI TC3/PHY D][CRTC:80:pipe A] DP link limits: pixel clock 1286010 kHz DSC on max lanes 4 max rate 810000 max pipe_bpp 24 max link_bpp 24.0000
[96745.396654] i915 0000:00:02.0: [drm:intel_dp_dsc_compute_config [i915]] No Valid pipe bpp for given mode ret = -22
[96745.396697] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [ENCODER:245:DDI TC3/PHY D] config failure: -22
[96745.396752] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:80:pipe A] enable: yes [failed]

[emersion]

To confirm, you could try to comment out this line in wlroots: https://gitlab.freedesktop.org/wlroots/wlroots/-/blob/34219b03342b1947f0a8e6ea3aab30663523a1e0/backend/drm/atomic.c#L377

And then reboot the whole machine to start from a clean state.

[supermarin]

Tried the above, and pretty much seeing the same issue. I'm not too familiar with DRM protocol to diagnose this properly.

How did you infer there was an issue with max_bpc? I understand that bpp and bpc are directly related and seeing a bunch of bpp stuff in the logs.

The display in question connects over DP1.4 and should support:

• max_bpp: 30 bits per pixel
• max_bpc: 10 bits per component (red, green, blue)

From the dmesg logs I can see:

[96705.959926] i915 0000:00:02.0: [drm:update_display_info.part.0 [drm]] [CONNECTOR:246:DP-1] Assigning EDID-1.4 digital sink color depth as 10 bpc.
...
[96705.960121] i915 0000:00:02.0: [drm:update_display_info.part.0 [drm]] [CONNECTOR:246:DP-1] ELD size 36, SAD count 0
[96705.960136] [drm:__displayid_iter_next [drm]] base revision 0x12, length 121, 0 0
[96705.960149] i915 0000:00:02.0: [drm:drm_edid_connector_update [drm]] [CONNECTOR:246:DP-1] tile cap 0x82, size 3008x3384, num tiles 2x1, location 0x0, vend APP
[96705.960165] [drm:__displayid_iter_next [drm]] base revision 0x12, length 121, 0 0
[96705.960179] [drm:__displayid_iter_next [drm]] base revision 0x12, length 121, 0 0
[96705.960192] [drm:__displayid_iter_next [drm]] base revision 0x12, length 121, 0 0
[96705.960204] [drm:__displayid_iter_next [drm]] base revision 0x12, length 121, 0 0
[96705.960218] [drm:drm_mode_object_put.part.0 [drm]] OBJ ID: 272 (1)
[96705.960236] [drm:drm_mode_object_put.part.0 [drm]] OBJ ID: 277 (1)
[96705.960252] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:246:DP-1] VRR capable: no
[96705.960300] i915 0000:00:02.0: [drm:intel_dp_set_edid [i915]] [CONNECTOR:246:DP-1] DFP max bpc 0, max dotclock 0, TMDS clock 0-0, PCON Max FRL BW 0Gbps

Then in this whole probing dance it never hits 30 but goes 16->24->12->19

[96705.962214] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 47 for 64 timeslots total bw 25920000 pixel clock 543084
[96705.962259] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 16 to VESA 15
[96705.962310] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 47 for 64 timeslots total bw 25920000 pixel clock 543084
[96705.962353] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 16 to VESA 15
[96705.962403] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 106 for 64 timeslots total bw 25920000 pixel clock 243885
[96705.962445] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 24 to VESA 15
[96705.962493] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 47 for 64 timeslots total bw 25920000 pixel clock 543022
[96705.962534] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 16 to VESA 15
[96705.962582] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 47 for 64 timeslots total bw 25920000 pixel clock 543033
[96705.962623] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 16 to VESA 15
[96705.962670] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 47 for 64 timeslots total bw 25920000 pixel clock 543074
[96705.962710] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 16 to VESA 15
[96705.962757] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 47 for 64 timeslots total bw 25920000 pixel clock 543084
[96705.962797] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 16 to VESA 15
[96705.962843] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 38 for 64 timeslots total bw 25920000 pixel clock 667423
[96705.962883] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 20 to VESA 15
[96705.962930] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 52 for 64 timeslots total bw 25920000 pixel clock 495000
[96705.962969] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 24 to VESA 15
[96705.963017] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 52 for 64 timeslots total bw 25920000 pixel clock 494836
[96705.963058] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 24 to VESA 15
[96705.963106] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 52 for 64 timeslots total bw 25920000 pixel clock 494918
[96705.963146] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 24 to VESA 15
[96705.963193] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 52 for 64 timeslots total bw 25920000 pixel clock 494969
[96705.963232] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 24 to VESA 15
[96705.963279] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 52 for 64 timeslots total bw 25920000 pixel clock 494867
[96705.963319] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 24 to VESA 15
[96705.963366] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 38 for 64 timeslots total bw 25920000 pixel clock 667320
[96705.963406] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 20 to VESA 15
[96705.963454] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 38 for 64 timeslots total bw 25920000 pixel clock 667392
[96705.963493] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 20 to VESA 15
[96705.963540] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 38 for 64 timeslots total bw 25920000 pixel clock 667423
[96705.963579] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 20 to VESA 15
[96705.963626] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 38 for 64 timeslots total bw 25920000 pixel clock 667361
[96705.963666] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 20 to VESA 15
[96705.963712] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 26 for 64 timeslots total bw 25920000 pixel clock 960451
[96705.963753] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 12 to VESA 12
[96705.963801] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 26 for 64 timeslots total bw 25920000 pixel clock 960133
[96705.963842] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 12 to VESA 12
[96705.963890] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 26 for 64 timeslots total bw 25920000 pixel clock 960297
[96705.963930] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 12 to VESA 12
[96705.963978] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 26 for 64 timeslots total bw 25920000 pixel clock 960390
[96705.964018] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 12 to VESA 12
[96705.964067] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 26 for 64 timeslots total bw 25920000 pixel clock 960194
[96705.964107] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 12 to VESA 12
[96705.964154] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 19 for 64 timeslots total bw 25920000 pixel clock 1322700
[96705.964194] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 19 to VESA 15
[96705.964241] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 19 for 64 timeslots total bw 25920000 pixel clock 1322504
[96705.964281] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 19 to VESA 15
[96705.964328] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 19 for 64 timeslots total bw 25920000 pixel clock 1322638
[96705.964367] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 19 to VESA 15
[96705.964414] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 19 for 64 timeslots total bw 25920000 pixel clock 1322700
[96705.964454] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 19 to VESA 15
[96705.964501] i915 0000:00:02.0: [drm:intel_dp_dsc_get_max_compressed_bpp [i915]] Max link bpp is 19 for 64 timeslots total bw 25920000 pixel clock 1322576
[96705.964541] i915 0000:00:02.0: [drm:intel_dp_dsc_nearest_valid_bpp [i915]] Set dsc bpp from 19 to VESA 15

In any case, max_bpc is somehow listed at 0 - not sure if that's assumed somewhere in the code or read through the connection.

@emersion Do you think I should try to force max_bpp:30 and max_bpc:10 in the code and see what that does?

[supermarin]

Tried hardcoding max_bpp 30 in the line you commented out, and let's say that didn't go well :joy: The display freezes when I try to launch sway from the tty.

[supermarin]

@emersion following up on this. Is there anything I can do to help drill this down further?

[supermarin]

A couple of updates:

• I've updated the kernel (6.8.7) and running on newest nixpkgs
• Installed GNOME side by side to see if it would work with the monitor

...and somehow both GNOME and sway work correctly now. Sway is on 1.9. This tells me that either there was a fix in the kernel that affected this behavior, or it has to do with launching sway through GNOME's display manager gdm.

Will uninstall GNOME again and see what happens without it & report back.

[emersion]

Yeah, sorry, no clue what's up here. Maybe try opening a bug report for the kernel drivers if it starts to break again.

[supermarin]

Very weird. After swayidle powered the output off and then back on, reproduced the issue and couldn't get 6k resolution. I'm thinking it's gdm that sets up the screen in correct resolution. Will remove them in a bit now and confirm the bug persists with sway only.

[supermarin]

ok confirmed, if launching sway directly from the tty or from a separate login manager (regreet), the issue is back here.

[emersion]

Hm, so Sway is doing something differently then. Can you (1) try Sway latest commit (see wiki for easy instructions) (2) try setting WLR_DRM_NO_MODIFIERS=1 before starting Sway (3) collecting drm_info logs in both GNOME and Sway so that we can compare?

[ayushnix]

I just got a Dell 6K monitor (U3224KB) and I'm unable to see its native resolution (6144X3456) listed in the swaymsg -t get_outputs. It looks like my issue might be similar to this issue so I'm adding my comment here. The monitor is connected with an HDMI 2.1 cable to an AMD RX 6400 GPU with 4GB VRAM on its HDMI 2.1 port. I tried this on both sway version 1.9 and master (2024-05-04).

I tried setting the native resolution using --custom and generated these DRM debug logs, which might help. Here are the sway debug logs.

I opened a nested sway session with the env var WLR_DRM_NO_MODIFIERS=1 but that doesn't list the native resolution either.

EDIT: I realized that the refusal of HDMI forum to let AMD implement an open source HDMI 2.1 implementation is probably the reason why I'm unable to get native resolution. If that's true, sorry for the noise.

[bl4ckb0ne]

[ 616.198517] [drm:create_validate_stream_for_sink [amdgpu]] Mode 6144x3456 (clk 889500) failed DC validation with error 6 (Encoder validation failure)

Might be a kernel issue

[supermarin]

@ayushnix can you try running an older version of Sway, like 1.8 just to double confirm?

@emersion unfortunately I haven't had time to rerun the tests with gdm. I'll need to wrap the sway binary to include the flags and logging since there's no control over launching it through gdm login manager.

[ayushnix]

I got a USB-C to DP 1.4 cable and I'm able to use my monitor with its native resolution (6144x3456) on sway version 1.9 without any issues so far. I was also able to use CVT-RB and CVT-RB2 modeline as well.

output 'DP-1' {
    scale 2
    # CVT-RB
    # modeline 1344.25 6144 6192 6224 6304 3456 3459 3464 3555 +hsync -vsync
    # CVT-RB2
    modeline 1327.579 6144 6152 6184 6224 3456 3541 3549 3555 +hsync -vsync
}

[supermarin]

@ayushnix what did you use to create modeline?

[ayushnix]

@supermarin https://tomverbeure.github.io/video_timings_calculator