Case expression and choice expression width mismatch

[sy2002]

Randomly found this while waiting for synth to complete and browsing log files.

Not sure if relevant, feel free to "Close as not planned" if not relevant:

[Synth 8-6044] Case expression and choice expression width mismatch, Case expression is 9 wide and choice expression is 8 wide ["M2M/vhdl/controllers/HDMI/video_out_clock.vhd":136]

It is about this 9-bit long case statement and these 8-bit long when statements:

        case '0' & addr is
          -- Desired frequency = 25.200 MHz
          -- CLKFBOUT_MULT_F   = 31.500
          -- DIVCLK_DIVIDE     = 5
          -- CLKOUT0_DIVIDE_F  = 5.000
          -- CLKOUT1_DIVIDE    = 25
          -- Actual frequency  = 25.200 MHz
          when x"00" => data := x"06" & x"1145" & x"1000";  -- CLKOUT5 Register 1
          when x"01" => data := x"07" & x"0000" & x"8000";  -- CLKOUT5 Register 2
          when x"02" => data := x"08" & x"1083" & x"1000";  -- CLKOUT0 Register 1

[MJoergen]

That is indeed a bug, although I think Vivado magically knows what I'm trying to do. Thanks for reporting it.