sy2002 / MiSTer2MEGA65

Framework to simplify porting MiSTer (and other) cores to the MEGA65
GNU General Public License v3.0
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Research 200 MHz HyperRAM for R4/R5 boards #36

Closed sy2002 closed 7 months ago

sy2002 commented 10 months ago

Looks like the newer HyperRAM chips on R4/R5 boards are able to cope with 200 MHz instead of the 100 MHz we are currently using. Would be a very welcome latency reduction and speed boost.

MJoergen commented 10 months ago

In the HyperRAM repository I've created a branch "mfj_175MHz". Link: https://github.com/MJoergen/HyperRAM/tree/mfj_175MHz

MJoergen commented 7 months ago

I'm not sure where this idea about a 200 MHz HyperRAM came from (maybe me?), and I think it's false.

The R3 board uses a IS66WVH8M8BLL-100B1LI (https://www.issi.com/WW/pdf/66-67WVH8M8ALL-BLL.pdf) chip (for U29), which indeed is rated to 100 MHz.

However, the R5 board uses a IS66WVH8M8DBLL-100B1LI (https://www.issi.com/WW/pdf/66-67WVH8M8DALL-BLL.pdf) chip (for U29), which is identical except it is "die revision D". Specifically, this chip is also only rated to 100 MHz.

I'm looking specifically at page 46 in the latter document: image

MJoergen commented 7 months ago

I'm guessing the confusion arose because the revision D does indeed come in a 200 MHz version (as can be seen above), but the R5/R6 boards only use the 100 MHz version.

MJoergen commented 7 months ago

However, what is confusing me is that section 10.3 of the revision D document above only details timing values for 200 MHz, 166 MHz, and 133 MHz versions. So timing details for the 100 MHz is not even documented!

sy2002 commented 7 months ago

@MJoergen Well, then we might want to close this "research" project here - shouldn't we?