build bitstream error: Left Record missing field (sys_rst)

[wisen]

when i follow the SOP to build bitstream, it occurs:

java.lang.reflect.InvocationTargetException
        at ... ()
        at starship.utils.stage.FIRRTLGenerator$.$anonfun$elaborate$2(RocketStage.scala:23)
        at starship.utils.stage.FIRRTLGenerator$.$anonfun$elaborate$4(RocketStage.scala:42)
        at ... ()
        at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
Caused by: chisel3.package$ChiselException: Connection between left (TestHarness.ddr: IO[XilinxVC707MIGPads]) and source (StarshipFPGATop.xilinxvc707mig_1: IO[XilinxVC707MIGIO]) failed @.sys_rst: Left Record missing field (sys_rst).
        at chisel3.internal.throwException$.apply(Error.scala:93)
        at chisel3.Data.bulkConnect(Data.scala:581)
        at chisel3.Data.$anonfun$$less$greater$1(Data.scala:737)
        at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.scala:18)

is there any workaround method?

[Phantom1003]

Hi, have you ever tried executing the command make patch to apply patches?

[zhouyangye1076]

There some patch in patch/rocket-chip-efpga-shells, maybe you should apply these patch on the repo/rocket-chip-fpga-shell submodule. run make patch directly will add some changes on repo/roscket-chip submodule for simulation flow, it is confliected with bitstream flow

[wisen]

@Phantom1003 @zhouyangye1076 Thanks for your advice. It is true that I did not perform the "make patch" step before，

root@wisen:/work/riscv-starship# make patch
find patch -name "*.patch" | \
        awk -F/ '{print \
                "(" \
                        "echo \"Apply " $0 "\" && " \
                        "cd repo/" $2 " && " \
                        "git apply --ignore-space-change --ignore-whitespace ../../" $0 \
                ")" \
        }' | sh
Apply patch/riscv-boom/1.patch
Apply patch/rocket-chip/1.patch
Apply patch/rocket-chip/2.patch
Apply patch/rocket-chip/3.patch
Apply patch/rocket-chip/4.patch
Apply patch/rocket-chip/5.patch
Apply patch/rocket-chip-fpga-shells/1.patch
Apply patch/rocket-chip-fpga-shells/2.patch
Apply patch/rocket-chip-fpga-shells/3.patch
Apply patch/rocket-chip-fpga-shells/4.patch
Apply patch/rocket-chip-fpga-shells/5.patch
Apply patch/rocket-chip-fpga-shells/6.patch

but after I performed this step, new problems appeared:

java.lang.reflect.InvocationTargetException
        at ... ()
        at starship.utils.stage.FIRRTLGenerator$.$anonfun$elaborate$2(RocketStage.scala:23)
        at starship.utils.stage.FIRRTLGenerator$.$anonfun$elaborate$4(RocketStage.scala:42)
        at ... ()
        at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
Caused by: java.lang.IllegalArgumentException: requirement failed: Connecting JTAG requires that debug module exists
        at scala.Predef$.require(Predef.scala:337)
        at sifive.fpgashells.shell.xilinx.vc707shell.HasDebugJTAG.connectDebugJTAG(VC707Shell.scala:77)
        at sifive.fpgashells.shell.xilinx.vc707shell.HasDebugJTAG.connectDebugJTAG$(VC707Shell.scala:75)
        at starship.fpga.TestHarness.connectDebugJTAG(VC707.scala:52)
        at starship.fpga.TestHarness.$anonfun$new$3(VC707.scala:71)

any new suggestions?

[zhouyangye1076]

''' STARSHIP_CONFIG ?= starship.fpga.StarshipFPGAConfig ''' in conf/build.mk should be changed as

STARSHIP_CONFIG ?= StarshipFPGADebugConfig

we add jtag connection in starshipFPGATop, but only add jtag configuration in StarshipFPGADebugConfig

[wisen]

When i fix all the workaround above this afternoon, and rebuild the project, arose a new issue :

[warn] repo/rocket-chip/src/main/scala/rocket/ICache.scala:500:25: Dynamic index with width 7 is too small for extractee of width 25
[warn]     val s1_vb = vb_array(Cat(i.U, s1_idx)) && !s1_slaveValid
[warn]                         ^
[warn] repo/rocket-chip/src/main/scala/rocket/CSR.scala:954:100: Dynamic index with width 8 is too large for extractee of width 64
[warn]   val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_lsbs), read_medeleg(cause_lsbs))
[warn]                                                                                                    ^
[warn] repo/rocket-chip/src/main/scala/rocket/CSR.scala:954:126: Dynamic index with width 8 is too large for extractee of width 64
[warn]   val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_lsbs), read_medeleg(cause_lsbs))
[warn]
[warn] repo/rocket-chip/src/main/scala/rocket/CSR.scala:955:80: Dynamic index with width 8 is too large for extractee of width 64
[warn]   val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_lsbs), read_hedeleg(cause_lsbs))
[warn]                                                                                ^
[warn] repo/rocket-chip/src/main/scala/rocket/CSR.scala:955:106: Dynamic index with width 8 is too large for extractee of width 64
[warn]   val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_lsbs), read_hedeleg(cause_lsbs))
[warn]                                                                                                          ^
[warn] repo/rocket-chip/src/main/scala/devices/debug/Debug.scala:1727:37: Dynamic index with width 1 is too large for extractee of width 1
[warn]     val hartHalted   = haltedBitRegs(selectedHartReg)
[warn]                                     ^
[warn] There were 6 warning(s) during hardware elaboration.
firrtl.transforms.BlackBoxNotFoundException: BlackBox '/xilinx/vc707/vsrc/vc707reset.v' not found. Did you misspell it? Is it in src/{main,test}/resources?
sbt.internal.LayeredClassLoader@314c14c4/xilinx/vc707/vsrc/vc707reset.v

make: *** [Makefile:71: /work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.fir] Error 1

[zhouyangye1076]

I have met this problem a few month ago, but I add a patch in my local repo, but I don't commit this change because of some reason. You can add a soft link in rocket-chip-fpga-shells. make a soft link 'src/main/resource' and link to ./xilinix. The chisel module in the rocket-chip-fpga-shell use the verilog module in /xilinix as blackbox, but chisel file organization think these verilog module in src/main/resource file path in default. So maybe you make this folder by yourself and link the xilinix to this folder

[wisen]

This afternoon, I continued the previous experiment, but the following errors occurred during the synthesis:

INFO: [Synth 8-6157] synthesizing module 'Rocket' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:55938]
INFO: [Synth 8-6157] synthesizing module 'IBuf' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:49603]
ERROR: [Synth 8-439] module 'MagicMaskerBlackbox' not found [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:49757]
ERROR: [Synth 8-6156] failed synthesizing module 'IBuf' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:49603]
ERROR: [Synth 8-6156] failed synthesizing module 'Rocket' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:55938]
ERROR: [Synth 8-6156] failed synthesizing module 'RocketTile' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:60452]
ERROR: [Synth 8-6156] failed synthesizing module 'TilePRCIDomain' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:64858]
ERROR: [Synth 8-6156] failed synthesizing module 'StarshipFPGATop' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.top.v:97390]
ERROR: [Synth 8-6156] failed synthesizing module 'TestHarness' [/work/riscv-starship/build/rocket-chip/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.testharness.v:290]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 3267.602 ; gain = 589.641 ; free physical = 3186 ; free virtual = 7026
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
270 Infos, 0 Warnings, 0 Critical Warnings and 8 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

    while executing
"source [file join $scriptdir "synth.tcl"]"
    (file "/work/riscv-starship/repo/rocket-chip-fpga-shells/xilinx/common/tcl/vivado.tcl" line 13)
INFO: [Common 17-206] Exiting Vivado at Fri Mar 22 10:44:54 2024...
make: *** [Makefile:182: /work/riscv-starship/build/vivado/Rocket.StarshipFPGATop.StarshipFPGADebugConfig.bit] Error 1

[Phantom1003]

Hi, it seems like you have installed all the patches. The missing MagicMaskerBlackbox module is used for stress testing the hardware during simulation, which is included from patch. This module uses DPI functions, it is not synthesizable. And since you focus on FPGA flow, it is not necessary. As @zhouyangye1076 suggested, you should only apply the patches for the FPGA flow. If you want to drop out the patches, you can checkout the rocket-chip submodule. We apologize for the confusion caused and will update the instructions to make them clearer.

[wisen]

Yes, when i rollback the patch under rocket-chip, then build bitstream successful, thanks for your guide. @Phantom1003 @zhouyangye1076

please close this issue, any other issue, i'll create the new.