sylefeb
commented
2 years ago Hi - indeed, resets are currently generated as synchronous; but it would be possible to add an algorithm modifier (e.g. similar to autorun see modifiers ) to request an asynchronous reset. I never quite encountered the use case, and defaulted to synchronous. Unsure what side effect the asynchronous reset could have (I think it should be ok, with all usual gotchas of those), I am curious to experiment.
Would a modifier provide what you need? (for instance declaring the algorithm as algorithm main(...) <async_reset> { ... } ?).
Side note: you can specify which signal to use as reset when instantiating an algorithm. For instance see the hdmi controller where rst is used as reset signal, and produced from a clean_reset algorithm.
Hello. I have question about how reset is added. I see that we don't mention resets in .ice files and they are added transparently in the generated verilog. However, I see it uses only Sync resets not Async ones. So, 1- Is there a reason for this? 2- Is there a way that I can use Async resets instead of Sync (without manually edit the output verilog code) Thanks