sylefeb / Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
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Missing template, dualport bram with byte masking #229

Closed rob-ng15 closed 2 years ago

rob-ng15 commented 2 years ago

I was looking to try to use a dualport bram with byte masking.

Created this file: _dualport_bram_wmaskbyte.v.in in the templates directory:

// SL 2019, MIT license
module %MODULE%(
input      [%WENABLE0_WIDTH%-1:0]             in_%NAME%_wenable0,
input      %DATA_TYPE% [%DATA_WIDTH%-1:0]     in_%NAME%_wdata0,
input      [%ADDR0_WIDTH%-1:0]                in_%NAME%_addr0,
input      [%WENABLE1_WIDTH%-1:0]             in_%NAME%_wenable1,
input      [%DATA_WIDTH%-1:0]                 in_%NAME%_wdata1,
input      [%ADDR1_WIDTH%-1:0]                in_%NAME%_addr1,
output reg %DATA_TYPE% [%DATA_WIDTH%-1:0]     out_%NAME%_rdata0,
output reg %DATA_TYPE% [%DATA_WIDTH%-1:0]     out_%NAME%_rdata1,
input      %CLOCK%0,
input      %CLOCK%1
);
(* no_rw_check *) reg %DATA_TYPE% [%DATA_WIDTH%-1:0] buffer[%DATA_SIZE%-1:0];
always @(posedge %CLOCK%0) begin
  out_%NAME%_rdata0 <= buffer[in_%NAME%_addr0];
  out_%NAME%_rdata1 <= buffer[in_%NAME%_addr1];
end
integer i;
always @(posedge %CLOCK%0) begin
  for (i = 0; i < (%DATA_WIDTH%)/8; i = i + 1) begin
    if (in_%NAME%_wenable0[i]) begin
      buffer[in_%NAME%_addr0][i*8+:8] <= in_%NAME%_wdata0[i*8+:8];
    end
    if (in_%NAME%_wenable1[i]) begin
      buffer[in_%NAME%_addr1][i*8+:8] <= in_%NAME%_wdata1[i*8+:8];
    end
  end
end
%INITIAL%
endmodule

However testing, via verilator, when invoked via

    $$config['dualport_bram_wmask_byte_wenable0_width'] = 'data'
    $$config['dualport_bram_wmask_byte_wenable1_width'] = 'data'
    dualport_bram uint16 ram<"dualport_bram_wmask_byte"> [16384] = {file("ROM/VBIOS.bin"), pad(uninitialized)};

always gives ram.rdata1 as 0x0000.

Would be a useful enhancement, if you can correct any errors in the above?

rob-ng15 commented 2 years ago

Apologies, the error was elsewhere, was truncating the readdata elsewhere to 16 bit. The above works in verilator. Will test on hardware.

Rob.