interleaving pipelined algorithms in host pipelines

[sylefeb]

There is currently no clean/simple way to interleave a pipelined algorithm into a host pipeline. This could be for instance:

• a dedicated syntax chaining the algorithm inside the host pipeline
• a signal indicating an output of a pipelined algorithm is ready
• other?

[sylefeb]

Related: example of chaining two pipelined algorithms from a parent https://github.com/sylefeb/Silice/blob/draft/tests/pipeline27.si