sylefeb / Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
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Combining declaration and always assignment #244

Open rob-ng15 opened 1 year ago

rob-ng15 commented 1 year ago

Presently, a "variable" to be always assigned a value ( unless overwritten in algorithm ) has to be declared, then always assigned.

uint1 OF = uninitialised; // OVERFLOW FLAG uint1 UF = uninitialised; // UNDERFLOW FLAG OF := 0; UF := 0; // HOLD AT ZERO

Would it be possible/desirable to combine the declaration and always assignment?

e.g.

unit OF := 0;

My caution is that we already have =, <: and <:: as possibilities, but was thinking from a code readability point of view, easier to declare and always assign a value together when commenting.

Rob.