search

sylefeb / Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
Other
1.3k stars 78 forks source link

Many boards share a common set of features, yet each board has its own define #246

Open sylefeb opened 1 year ago

sylefeb commented 1 year ago

The example projects tend to be built for boards, using board-specific defines (ICEBREAKER, ULX3S) while many boards share a common FPGA and feature set (ice40, ecp5, etc.). Often only the pinout/clock differ.

Should we get a more fine grained define system? This could be the opportunity to also get an improved (consistent) PLL system and revise/cleanup the pinout names...

rob-ng15 commented 1 year ago

Hello,

This does sound like a good idea, especially for adding extra boards, e.g. ulx3s and ulx4m will be pretty similar, differing I/O pinouts, but the same FPGA chip as you stated.

As for how, fpga.board.variant? So, the ulx3s would be ecp5.ulx3s.85f ?

Rob.

On Sun, 5 Mar 2023 at 17:50, sylefeb @.***> wrote:

The example projects tend to be built for boards, using board-specific defines (ICEBREAKER, ULX3S) while many boards share a common FPGA and feature set (ice40, ecp5, etc.). Often only the pinout/clock differ.

Should we get a more fine grained define system? This could be the opportunity to also get an improved (consistent) PLL system and revise/cleanup the pinout names...

— Reply to this email directly, view it on GitHub https://github.com/sylefeb/Silice/issues/246, or unsubscribe https://github.com/notifications/unsubscribe-auth/AN4SYTZFAR5Y66MLBELNGM3W2TG7BANCNFSM6AAAAAAVQJM5FQ . You are receiving this because you are subscribed to this thread.Message ID: @.***>

goran-mahovlic commented 1 year ago

@sylefeb Thank you for accepting pull request for ulx4m! As for board versions on ulx4m for now we will have

ulx4m-ls (ECP5 SDRAM) and ulx4m-ld (ECP5 DDR3) and each version will have revisions.

Goran