suarezvictor
commented
1 year ago I think a good way to save many cycles is as follows.
In the following code, there are many else blocks that the only thing they do is to set next state:
module M_uart_tx (
in_data,
in_clock_counter,
out_tx_pin,
out_out_valid,
in_run,
out_done,
reset,
out_clock,
clock
);
input [7:0] in_data;
input signed [31:0] in_clock_counter;
output [0:0] out_tx_pin;
output [0:0] out_out_valid;
input in_run;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
reg signed [31:0] _d_t1;
reg signed [31:0] _q_t1;
reg [7:0] _d___block_3_mask;
reg [7:0] _q___block_3_mask;
reg [0:0] _d_tx_pin;
reg [0:0] _q_tx_pin;
reg [0:0] _d_out_valid;
reg [0:0] _q_out_valid;
reg [3:0] _d__idx_fsm0,_q__idx_fsm0;
assign out_tx_pin = _q_tx_pin;
assign out_out_valid = _q_out_valid;
assign out_done = (_q__idx_fsm0 == 0)
;
`ifdef FORMAL
initial begin
assume(reset);
end
assume property($initstate || (in_run || out_done));
`endif
always @* begin
_d_t1 = _q_t1;
_d___block_3_mask = _q___block_3_mask;
_d_tx_pin = _q_tx_pin;
_d_out_valid = _q_out_valid;
_d__idx_fsm0 = _q__idx_fsm0;
// _always_pre
(* full_case *)
case (_q__idx_fsm0)
1: begin
// _top
_d_t1 = in_clock_counter+1;
_d_tx_pin = 0;
_d_out_valid = 1;
_d__idx_fsm0 = 2;
end
2: begin
// __while__block_1
if (1&&in_clock_counter-_q_t1<0) begin
// __block_2
// __block_4
_d_out_valid = 0;
// __block_5
_d__idx_fsm0 = 2;
end else begin
_d__idx_fsm0 = 3;
end
end
3: begin
// __block_3
_d_t1 = _q_t1+1;
_d___block_3_mask = 1;
_d__idx_fsm0 = 4;
end
4: begin
// __while__block_6
if (_q___block_3_mask!=0) begin
// __block_7
// __block_9
// __block_10
_d_tx_pin = (in_data&_q___block_3_mask)!=0;
_d_out_valid = 1;
_d__idx_fsm0 = 8;
end else begin
_d__idx_fsm0 = 5;
end
end
8: begin
// __while__block_11
if (1&&in_clock_counter-_q_t1<0) begin
// __block_12
// __block_14
_d_out_valid = 0;
// __block_15
_d__idx_fsm0 = 8;
end else begin
_d__idx_fsm0 = 9;
end
end
5: begin
// __block_8
_d_tx_pin = 1;
_d_out_valid = 1;
_d__idx_fsm0 = 6;
end
9: begin
// __block_13
_d_t1 = _q_t1+1;
// __block_16
_d___block_3_mask = _q___block_3_mask<<1;
// __block_17
_d__idx_fsm0 = 4;
end
6: begin
// __while__block_18
if (1&&in_clock_counter-_q_t1<0) begin
// __block_19
// __block_21
_d_out_valid = 0;
// __block_22
_d__idx_fsm0 = 6;
end else begin
_d__idx_fsm0 = 0;
end
end
7: begin
// __block_20
_d__idx_fsm0 = 0;
end
0: begin
end
default: begin
_d__idx_fsm0 = {4{1'bx}};
`ifdef FORMAL
assume(0);
`endif
end
endcase
// _always_post
// pipeline stage triggers
end
always @(posedge clock) begin
_q_t1 <= _d_t1;
_q___block_3_mask <= _d___block_3_mask;
_q_tx_pin <= _d_tx_pin;
_q_out_valid <= _d_out_valid;
_q__idx_fsm0 <= reset ? 0 : ( ~in_run ? 1 : _d__idx_fsm0);
end
endmoduleAny time that a block jumps to a next state (doing nothing else), the code block of the target state can be incorporated instead of just jumping, saving a clock cycle. Doing that incorporation may leave states that are not referenced anymore in other block, so they can be safely deleted.
In practice, this UART example is taking more cycles than really needed, and applying the above may get it to the optimum amount of cycles (i.e., producing up to a bit per cycle)
Original Silice code, for reference:
algorithm uart_tx(
input uint8 data,
output uint1 tx_pin,
output uint1 out_valid,
input int32 clock_counter
)
{
int32 t1 = uninitialized;
t1 = clock_counter + 1; //constant may change for other baudrate
tx_pin = 0;
out_valid = 1;
while(clock_counter - t1 < 0)
{ out_valid = 0; }
t1 = t1 + 1;
uint8 mask = uninitialized;
mask=1;
while(mask!=0)
{
tx_pin = (data & mask) != 0;
out_valid = 1;
while(clock_counter - t1 < 0)
{ out_valid = 0; }
t1 = t1 + 1;
mask=mask<<1;
}
tx_pin = 1;
out_valid = 1;
while(clock_counter - t1 < 0)
{ out_valid = 0; }
}
sylefeb
rob-ng15
at91rm9200
Ideally there would be no such states, in particular this needlessly increases the number of states in the FSM and the index width.
Here is an example:
Verilog (relevant part):
State 3 is left over (added but unused). This might only affect the case solved after #247 (jump to termination state), to be confirmed.