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sylefeb / Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
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$$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */ #268

Open FPGAEveryday opened 7 months ago

FPGAEveryday commented 7 months ago

I am not sure how hard this one is to fix, but if I have either of the following in my board file Verilog:

`ifdef SOMETHING_NOT_DEFINED
$$ SOME_VARIABLE = 16
`endif

or

/*
$$ SOME_VARIABLE = 16
*/

SOME_VARIABLE will still be defined to 16 for the Silice code. I had wired through support for two different parallel OLED displays in my board verilog file with one commented out - the commented out block was after and set some of the same variables, and they still got set even though it was commented out.