Enhancement of declaration of and usage of always assignments

[rob-ng15]

It is quite common in Silice to have something like...

uint1   COMMIT = uninitialized;
.
.
.
COMMIT := 0;

Is there any reason why these two lines cannot be combined into say...

uint1   COMMIT := 0;

Similarly, but not as important, to me anyway, as the above, in a unit definition, there are output lines that are always assigned later in the unit, the req_read and req_write in this example. Can they be marked as such in the unit definition?

unit CPU6502(
    input   uint1   TIMER_irq,
    input   uint1   UART_irq,

    output  uint16  out_address,
    output  uint1   out_wrappage,
    output  uint24  out_data,
    input   uint24  in_data,

    output  uint3   req_mask,
    output  uint1   req_read,
    output  uint1   req_write,
    input   uint1   mem_busy,

    input   uint1   RUN,
    input   uint1   RESET,
    input   uint1   DEBUG

as...

unit CPU6502(
    input   uint1   TIMER_irq,
    input   uint1   UART_irq,

    output  uint16  out_address,
    output  uint1   out_wrappage,
    output  uint24  out_data,
    input   uint24  in_data,

    output  uint3   req_mask,
    output  uint1   req_read := 0,
    output  uint1   req_write := 0,
    input   uint1   mem_busy,

    input   uint1   RUN,
    input   uint1   RESET,
    input   uint1   DEBUG