Generate RISC-V instruction decoder from ISA descriptor

[jserv]

There is some relevant documentation included with the current RISC-V instructions decoding implementation. The maintenance and verification, however, are not straightforward. Instead, we may describe how RISC-V instructions are encoded in human readable form; a code generator will then convert this information into C code. See make_decoder.py from arviss and HiSimu for reference.

Expected output:

1. Create src/instructions.in which contains the following:

   # format of a line in this file:
   # <instruction name> <args> <opcode>
   #
   # <opcode> is given by specifying one or more range/value pairs:
   # hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
   #
   # <args> is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi,
   # shamtw, shamt, rm
   # rv32i
   beq     bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3
   bne     bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3
   blt     bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3
   bge     bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3
   bltu    bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3
   bgeu    bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3

2. Prepare scripts/gen-decoder.py (other scripting languages are acceptable.) which can convert from the above into the corresponding C implementation.
3. Modify build system and src/decode.c to be aware of the above changes.
4. Create an entry in directory docs which describe the high level idea and the way to describe more extensions.

[jserv]

rvjit provides similar code generation. See its scripts.

[jserv]

Google's mpact-riscv offers ISA description for the RV32/RV64 architecture. See riscv/*.isa for details.

[jserv]

riscvhpp is a user-level C++17 header-only RISC-V emulator generator using riscv-opcodes.

[jserv]

Google's mpact-riscv offers ISA description for the RV32/RV64 architecture. See riscv/*.isa for details.

MPACT-Sim provides a set of tools and C++ classes that makes it easier to write instruction level simulators for a wide range of architectures.

Build instructions:

$ git clone https://github.com/google/mpact-riscv
$ cd mpact-riscv
$ bazel build //...

[jserv]

Cavatools simulates a multi-core RISC-V machine. It provides "uspike," which is a RISC-V instruction set interpreter. Python scripts extract instruction bit encoding and execution semantics from the official GitHub repository.