Implement RISC-V Vector Extension

[howjmay]

RISC-V "V" Vector Extension (shorten as RVV) is the instruction extension that introduces vector process capabilities to RISCV.

The staged goal of this issue is to explore the possibility to run RVV instructions with rv32emu.

• Configure vtype and vl CSRs with vsetvli/vsetivli/vsetvl. This is required because RVV vector register is variable-legnth.
• Unit-Stride store/load instructions. This can help us to build the minimum POC.
• Basic integer ALU instructions ( vadd, vsub, vmin, vmax, vand, vor, vxor) and permutation instructions (vrgather, vslideup, vslidedown)

To achieve the goals we need to

1. Implement the instruction decoder (in decode.c). This decoder should be able to decode all three instructions formats (valu, vcfg, vmem)
2. Add the corresponding CSRs (vl, vtype)
3. Implement RVV instructions into custom IRs. Some of RVV may be implemented as a loop of basic instructions (like vadd from add). To maintain the readability of throughout the entire codebase, adding a new src file rvv_template.c for the RVV's IRs may be a better idea.
4. Study the further implementations (exception handling, rounding mode, float-points, comparison, mask instructions, etc.)

We can refer the following resource

1. RVV spec https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc
2. instruction tables https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/v-inst-table.edn
3. alu instructions formats https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/valu-format.edn
4. vector configuration instructions format https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/vcfg-format.edn
5. Spike's bit masks for decoding instructions https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/encoding.h

[howjmay]

the size of rv_insn.opcode may need to be extended

[howjmay]

Saw another tool may benefit us from testing https://github.com/hushenwei2000/rvv-atg