Closed blackgeorge-boom closed 1 year ago
Looking at how the INC32r
/DEC32r
is converted into LEA
instructions in X86InstrInfo::convertToThreeAddress
:
case X86::INC32r: {
...
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
(Is64Bit ? X86::LEA64_32r : X86::LEA32r);
We go directly to LEA64_32r
in the case of 64-bit subtargets, instead of LEA32r
. The former uses 64-bit registers as arguments, even though our INC32r
instruction requires just 32 bits. The register usage is the same essentially, but for example, if we spill these registers we end up in 8-byte spills in the first case, instead of 4-byte spills.
The reason that LEA32r
is avoided is that when we want to use 32-bit operands, the extra 0x67
prefix is needed to encode the instruction: https://stackoverflow.com/questions/59153772/address-size-override-prefix-in-64-bit-or-using-64-bit-registers.
For now, we can enforce the use of LEA32r
instead.
X86 leverages the
LEA64_32r
instruction insidesort
:but then has to spill
rax
as an 8-byte value. Whereas AArch64:spills a 4-byte value.