Closed blackgeorge-boom closed 1 year ago
X86 isel
%8:fr64 = CMPSDrr %3:fr64(tied-def 0), killed %7:fr64, 0, debug-location !28; main.c:18:6
%9:vr128 = COPY %8:fr64, debug-location !28; main.c:18:6
%10:vr128 = MOVSDrm $rip, 1, $noreg, %const.0, $noreg, debug-location !28 :: (load 8 from constant-pool); main.c:18:6
%11:vr128 = PANDrr %9:vr128(tied-def 0), killed %10:vr128, debug-location !28; main.c:18:6
%12:vr128 = COPY %3:fr64, debug-location !28; main.c:18:6
%13:vr128 = PANDNrr %9:vr128(tied-def 0), killed %12:vr128, debug-location !28; main.c:18:6
%14:vr128 = PORrr %13:vr128(tied-def 0), killed %11:vr128, debug-location !28; main.c:18:6
Using vector types of two double fp values, X86 ends up using the 128-bit SSE xxm
registers, which are spilled in the stack using 16 bytes:
...
501062: andpd xmm0,xmm1
501066: andnpd xmm1,xmm2
50106a: orpd xmm1,xmm0
50106e: movapd XMMWORD PTR [rbp-0x20],xmm1
...
While AArch64 uses scalar 64-bit fp operands:
...
501060: fcsel d0, d0, d1, eq
501064: str d0, [sp, #0x10]
...