Closed blackgeorge-boom closed 10 months ago
The cause behind the different live interval weights are probably some gaps inside the slot numbering, because of different instruction removals that precede greedy
.
AArch64:
16B %4:gpr32 = COPY $w4
32B %3:gpr32 = COPY $w3
48B %2:gpr32 = COPY $w2
64B %1:gpr32 = COPY $w1
80B ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
112B $x0 = MOVaddr target-flags(aarch64-page) @main__str__c__, target-flags(aarch64-pageoff, aarch64-nc) @main__str__c__
X86:
0B bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000); %bb.2(37.50%), %bb.1(62.50%)
liveins: $esi, $edx, $ecx, $r8d
16B MOV32mr %stack.0, 1, $noreg, 0, $noreg, $r8d :: (store 4 into %stack.0)
32B MOV32mr %stack.1, 1, $noreg, 0, $noreg, $ecx :: (store 4 into %stack.1)
48B %23:gr32 = COPY $edx
64B %1:gr32 = COPY $esi
80B ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
144B $rdi = LEA64r $rip, 1, $noreg, @main__str__c__, $noreg
The last instructions seem further apart in the two architectures, even though they aren't. This could be fixed by "packing" the slot indexes of instructions right before greedy
.
An attempt for that is already underway in LLVM, which we will try to add to our LLVM as well: https://github.com/llvm/llvm-project/pull/67038
Examining the
regalloc
debug info, we see that the following corresponding registers are allocated differently. This is because of different live interval weights (calculated asUseDefFreq / (Size + 25*SlotIndex::InstrDist)
) that lead to different evictions:AArch64
X86