systems-nuts / unifico

Compiler and build harness for heterogeneous-ISA binaries with the same stack layout.
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Load from stack behaves differently due to remat rules #295

Closed blackgeorge-boom closed 10 months ago

blackgeorge-boom commented 10 months ago
#include <stdio.h>

void results(char *name, char class, int n1, int n2, int n3, niter, char *optype)
{
    if (n3 == 0) {
        long nn = n1;
        if (n2 != 0)
            nn *= n2;
        printf("%ld\n", nn);
    }
    else
        printf("%d%d%d\n", n1, n2, n3);

    printf("%s\n", optype);

}

int main() {
    results("IS", 'S', 1, 64, 0, 3, "keys ranked");

    return 0;

}
make clean; make stackmaps-check -j10 OBJDUMP_FLAGS= OPT_LEVEL=-O1

WARNING: results: callsite 0, value locations 1/1 have different location offset or  different constant (-32 vs. 16)
WARNING: results: callsite 1, value locations 0/0 have different location offset or  different constant (-40 vs. -32)
WARNING: results: callsite 1, value locations 3/3 have different location offset or  different constant (-32 vs. 16)
ERROR: stackmaps in 'main_aarch64_aligned.out' & 'main_x86_64_aligned.out' differ - different stack layout!
make: *** [../../common/common.mk:248: stackmaps-check] Error 1
blackgeorge-boom commented 10 months ago

Debugging regalloc:

arm

%22:gpr64 = LDRXui %fixed-stack.0, 0 :: (load 8 from %fixed-stack.0, align 16)

selectOrSplit GPR64:%22 [64r,296r:0)[352B,488r:0)  0@64r weight:2.623377e-03 w=2.623377e-03
RS_Spill Cascade 0
Inline spilling GPR64:%22 [64r,296r:0)[352B,488r:0)  0@64r weight:2.623377e-03
From original %6
Merged spilled regs: SS#0 [64r,296r:0)[352B,488r:0)  0@x weight:0.000000e+00
spillAroundUses %22
    rewrite: 64r    %26:gpr64 = LDRXui %fixed-stack.0, 0 :: (load 8 from %fixed-stack.0, align 16)

    spill:   72r    STRXui killed %26:gpr64, %stack.0, 0 :: (store 8 into %stack.0)
Checking redundant spills for 0@296r in %24 [296r,312r:0)  0@296r weight:2.774725e-03
Merged to stack int: SS#0 [64r,312r:0)[352B,488r:0)  0@x weight:0.000000e+00
Checking redundant spills for 0@312r in %23 [312r,352B:0)[504r,528B:1)[528B,624r:2)  0@312r 1@504r 2@528B-phi weight:5.430107e-03
Merged to stack int: SS#0 [64r,488r:0)  0@x weight:0.000000e+00
    folded:   296r  %24:gpr64 = LDRXui %stack.0, 0 :: (load 8 from %stack.0)
Checking redundant spills for 0@488r in %25 [488r,504r:0)  0@488r weight:4.508928e-03
Merged to stack int: SS#0 [64r,504r:0)  0@x weight:0.000000e+00
Checking redundant spills for 1@504r in %23 [312r,352B:0)[504r,528B:1)[528B,624r:2)  0@312r 1@504r 2@528B-phi weight:5.430107e-03
Merged to stack int: SS#0 [64r,528B:0)  0@x weight:0.000000e+00
    folded:   488r  %25:gpr64 = LDRXui %stack.0, 0 :: (load 8 from %stack.0)
queuing new interval: %26 [64r,72r:0)  0@64r weight:INF

x86

%25:gr64 = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)

selectOrSplit GR64:%25 [64r,344r:0)[400B,552r:0)  0@64r weight:1.211031e-03 w=1.211031e-03
RS_Spill Cascade 0
Inline spilling GR64:%25 [64r,344r:0)[400B,552r:0)  0@64r weight:1.211031e-03
From original %6
    remat:  340r    %29:gr64 = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
            344e    %27:gr64 = COPY killed %29:gr64

    remat:  548r    %30:gr64 = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
            552e    %28:gr64 = COPY killed %30:gr64

All defs dead: dead %25:gr64 = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
Remat created 1 dead defs.
Deleting dead def 64r   dead %25:gr64 = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
0 registers to spill after remat.
queuing new interval: %29 [340r,344r:0)  0@340r weight:INF
queuing new interval: %30 [548r,552r:0)  0@548r weight:INF

We see that the load from the fixed stack is regalloced differently.