BT compilation error with `-DUNIFICO_INSTR_EXTENSION`

[blackgeorge-boom]

make clean
make z_solve_opt.ll -j10 OBJDUMP_FLAGS= OPT_LEVEL=-O1
llc -function-sections -data-sections -no-sm-warn -relocation-model=pic --trap-unreachable -optimize-regalloc -fast-isel=false -disable-machine-cse -disable-block-align --mc-relax-all -aarch64-csr-alignment=8 -align-bytes-to-four -reg-scavenging-slot -align-objects-to-four -pack-indexes -enable-misched=false -mattr=+simple-reg-offset-addr -mattr=-multiply-with-imm,+aarch64-sized-imm -mattr=-non-zero-imm-to-mem -disable-gr32temp-inflate -mattr=+aarch64-constant-cost-model -x86-enable-simplify-cfg -mattr=+force-vector-mem-op,+avoid-opt-mul-1,+avoid-select-to-fsetcc -no-x86-call-frame-opt -disable-x86-frame-obj-order -enable-lea32 -mul-constant-optimization=false -march=x86-64 -filetype=obj -o z_solve_x86_64_init.o z_solve_opt.ll

LLVM ERROR: Cannot emit physreg copy instruction

[blackgeorge-boom]

Somehow we end up with this instruction:

  renamable $rax = COPY renamable $ecx, implicit killed $rcx

[blackgeorge-boom]

• The issue is that we've modified how MOVSX64rr32 works:

def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
                    "movs{lq|xd}\t{$src, $dst|$dst, $src}",
                    []>,
                    Sched<[WriteALU]>, Requires<[In64BitMode]>;

but other instructions, like the ISD:SIGN_EXTEND_INREG, might use this MIR instruction with a 32-bit argument.

• The problem was in this case:

def : Pat<(sext_inreg GR64:$src, i32),
          (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;

• This would give a 32-bit argument in MOVSX64rr32.

I've patched our LLVM to fix this.