Closed MenezesM closed 2 years ago
An AXIS to AXIS within the FPGA (created by the system) will fail if destination port is the same, because the interconnect name is the same.
For example if the block has a AXI input called begin_r then it will create a interconnected called axis_i_beginbeing for both.
An AXIS to AXIS within the FPGA (created by the system) will fail if destination port is the same, because the interconnect name is the same.
For example if the block has a AXI input called begin_r then it will create a interconnected called axis_i_beginbeing for both.