While benchmarking SPI I noticed that it was way slower than anticipated, around 3.5MB/s.
It's apparently caused by the FIFO's bus which is very slow from the CPU. Adding DMA restored the full 50MB/s speed.
For the SD controller, I also had to enable its internal DMA and fix the clocks to reach its full speed (~23MB/s on 4 bit).
Turns out FAT is very slow on SD because it makes a lots of small (4KB) reads. I added caching support to work around this, halving the load time to around 500ms, from 1200-800ms depending on the card. Using the Neon unit for memcpy also helped.
I've merged both linker files, they are now passing through the pre-processor to generate addresses.
I'll probably do another PR for cleanup and fixing up DDR mode for eMMC.
[I] SHMC: SD card detected
[D] FATFS: f_mount OK
[I] FATFS: read sun8i-t113-mangopi-dual.dtb addr=44000000
[D] FATFS: read in 1ms at 24.67MB/S
[I] FATFS: read zImage addr=44800000
[D] FATFS: read in 121ms at 44.71MB/S
[D] FATFS: f_mount unmount OK
[D] FATFS: done in 539ms
[I] SPI-NAND: W25N01GV detected
[D] SPI-NAND: dt blob: Copy from 0x00040000 to 0x44000000 size:0x000062b1
[I] SPI-NAND: read dt blob of size 25265 at 46.00MB/S
[D] SPI-NAND: Image: Copy from 0x00080000 to 0x44800000 size:0x00548700
[I] SPI-NAND: read Image of size 5539584 at 49.00MB/S
Another massive PR, sorry :)
While benchmarking SPI I noticed that it was way slower than anticipated, around 3.5MB/s. It's apparently caused by the FIFO's bus which is very slow from the CPU. Adding DMA restored the full 50MB/s speed.
For the SD controller, I also had to enable its internal DMA and fix the clocks to reach its full speed (~23MB/s on 4 bit). Turns out FAT is very slow on SD because it makes a lots of small (4KB) reads. I added caching support to work around this, halving the load time to around 500ms, from 1200-800ms depending on the card. Using the Neon unit for memcpy also helped.
I've merged both linker files, they are now passing through the pre-processor to generate addresses.
I'll probably do another PR for cleanup and fixing up DDR mode for eMMC.