ROM Update

[bossebandowski]

The migration from chisel2 to chisel3 was causing an inefficient ROM implementation with timing issues. This is now fixed and the patch includes the following changes:

• a new read function of the BOOTAPP file that returns a scala Array tuple instead of a chisel Vec
• a new BlackBoxRom class that parses the Array tuple into valid Verilog code and wraps it in a black box
• minor updates to the Fetch stage of patmos to match the changes
• updates to all quartus project files to include a new file BlackBoxRom.v that is created during make gen

Tested with blinking in emulator, and the bootloader on an FPGA

[schoeberl]

Nice work!