Add Skywater SRAM model

[tjarker]

Adds the verilog model of a 1kiB dual port SRAM. In Chisel the model is used in the SRAM module which combines as many SRAM's as needed to create a memory of arbitrary width and depth.

In the MemBlock module, commonly used throughout the patmos design as a basic memory building block, a conditional block is added to select between using the normal SyncReadMem or SRAM.

The verilog file of the SRAM model was added to the quartus project file for the DE2-115 and to the vivado project for the basys3.

[schoeberl]

Nice addition. We should have the selection as a parameter in the configuration file (the .xml file)