tabemann
commented
6 months ago I have made some changes to docs/words/pio.md to clarify what you mention. I also updated cyw43_spi.fs and it works fine with the change. (Now I need to figure out why my Pico W is getting horrible ping times as of today, which it was before making the change and still is since making the change, but that is another story. I don't think it is an issue with my Pico W, because when I try to git push to GitHub it's also really slow right now.)
Thanks for catching all this, Travis
These might be two separate issues, but they are connected. The PIO documentation wording is somewhat misleading when discussing side-set. It starts out by saying that PIO state machines may either have an optional delay in the instructions or a side-set. That's misleading because you can in fact have both, with the available 5 bits split between the two functions. The last sentence of the paragraph does say that. A related item is the
sm-sideset-high-enable!feature. The description is rather unclear. What this does is change the meaning of the high order bit in the delay/sideset field to be "sideset enable". That reduces the number of actual sideset bits available by one, and the high bit now means "don't do side-set" if 0, and "do side-set" if 1. It allows you to write programs where side-set is mentioned only on some instructions. "don't do side-set" means no change to the side-set pins.This ties into the PIO code in cyw43_spi.fs, which defines SIDE_1 to be 31. But that sets all the sideset/delay bits, and the sideset bit count is only 1. So the sideset pin value is taken from the top bit of those 5, and the remaining 4 bits are delay. That means the instruction with SIDE_1 on it has a 15 cycle delay on it. Is that intended? I assume not. I changed the line in question to read
$10 constant SIDE_1which sets the delay portion to zero. Pico W WiFi still seems to be quite happy so I guess the delay was not intended.