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taichi-ishitani / rggen

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
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Quartus crash #117

Closed adrianf0 closed 5 years ago

adrianf0 commented 5 years ago

The RTL code generated for an example register specification ( sample.xls ) crashes Quartus.

Tested with Quartus 18.0.0 Standard Edition (it has a limited support for SystemVerilog).

taichi-ishitani commented 5 years ago

Hi @adrianf0 , Thank you for using RgGen tool and opening the issue ! I need detail information to investigate the issue. Can you give me the log file?

adrianf0 commented 5 years ago

Hi @taichi-ishitani , thank you for your tool!

I am enclosing a simple project I have built quickly. I used a register specification from conf/samples.csv. It's a simplified version of your samples.xls from which I removed arrays: Verilog doesn't support arrays in port section and Quartus (and a quite few other tools with limited support of SystemVerilog) needs a top-level module without interfaces in a port declaration (check: #118 ).

Setting _rtl/topVerilogwrappper.v as top and adding all other sources to a Quartus project makes it crashing during synthesis.

Problem Details Error: Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/verilog/veriname.cpp, Line: 640 ...

It seems to crash during the synthesis of the rggen-building-block-rt library.

I have also tried to simulate quickly the design in Questa. Unfortunately, it fails, claiming there is a bug in a file generated by RgGen:

# ** Fatal: (vsim-3695) ../rtl/block_0.sv(37): The interface port 'bus_if' must be passed an actual interface. Time: 0 ns Iteration: 0 Instance: /topVerilogwrapper/top/block/u_host_if File: ../rggen-building-block-rtl/rggen_host_if_axi4lite.sv FATAL ERROR while loading design Error loading design

ReGenTry.zip

taichi-ishitani commented 5 years ago

Hi @adrianf0 , Thank you for your detail information.

Currently, RgGen supports APB only, AXI4 Lite is not supported. Can you edit configuration.yaml, change the host_if from axi4lite to apb and try again?

Detail:

I have not yet implemented the internal bus bridge module for AXI Lite. It has port definition only.

However, its port definition does not match current RgGen implementation. (Please refer the internal bus bridge for APB to know the current RgGen implementation.)

Therefore, the instantiation and the definition are not matched so Quartus crashed.

If you need to use AXI4 Lite, I will implement the bridge module during this week end.

taichi-ishitani commented 5 years ago

Hi @adrianf0 ,

I implemented the bus bridge module for AXI4 Lite and committed it to the development branch. https://github.com/taichi-ishitani/rggen-building-block-rtl/commit/a1b35abded60a600be6674534199e22aa5f268f0

Following commands are to get the latest bridge module:

$ cd rggen-building-block-rtl
$ git pull
$ git checkout implementing_axi4lite_bridge

Also I updated your generated code and wrapper modules for your trial. RgGen.zip

Could you please try to use the latest bridge module and the generated code? I will commit the latest bridge module to master branch after confirming success of your trial.

adrianf0 commented 5 years ago

Hi @taichi-ishitani Thank you for a prompt reply and a bugfix. In the latest version, Quartus complains that:

Error (10709): SystemVerilog error at block_0.sv(3): parameter with complex/aggregate value must have a type

The fix is to change in block_0: module block_0 #( parameter ACCESS_PRIORITY = rggen_rtl_pkg::RGGEN_WRITE to module block_0 #( parameter rggen_rtl_pkg::rggen_direction ACCESS_PRIORITY = rggen_rtl_pkg::RGGEN_WRITE Could you fix it in RgGen?

taichi-ishitani commented 5 years ago

Hi @adrianf0 , Thank you for your feedback. This is RgGen's bug. I'm fixing it now.

taichi-ishitani commented 5 years ago

After fixing block_0 module, does Quartus synthesis succeed?

adrianf0 commented 5 years ago

Yes, by adding manually the datatype, the whole design passes Quartus synthesis (yet still to be confirmed whether it work in hardware actually). How can I make use of your bugfixes? Will you push changes upstream so you I call gem update or there is another way (I am new to Ruby)?

taichi-ishitani commented 5 years ago

I have uploaded the latest RgGen to rubygems. You can get it by gem update rggen command.

adrianf0 commented 5 years ago

I confirm that using the latest RgGen (0.7.2) and checking out _implementing_axi4litebridge branch of rggen-building-block-rtl I can pass synthesis in Quartus (18.0.0).

taichi-ishitani commented 5 years ago

Good ! Thanks again for your using RgGen and opening the issue !!