Error when elab with Vivado

[aignacio]

Hi, I'm trying to build with Vivado 2020.1 and I'm seeing the following error:

ERROR: [VRFC 10-396] cannot assign a string to an unpacked type [/mnt/hgfs/test/projects/demo/tvip-axi/src/tvip_axi_monitor_base.svh:187]
WARNING: [VRFC 10-2663] foreach loop violates IEEE 1800 syntax [/mnt/hgfs/test/projects/demo/tvip-axi/tvip-common/src/tvip_item_waiter.svh:38]

Do you know why it's complaining with this?

[taichi-ishitani]

Hi @aignacio , Thank you for opening this issue! I've confirmed that tvip-axi can be compiled by Synospsy VCS and Cadence Xcelium simulators. Therefore, I think these error and warning are caused by bug of Vivado Simalator.

[taichi-ishitani]

@aignacio , I'd like you to report this issue to Xilinx if you can. Can you close this ticket if you have no topic?

[aignacio]

Hi @taichi-ishitani , here's the question in the Xilinx's forum, let's wait for their feedback first, before closing it....

https://forums.xilinx.com/t5/Simulation-and-Verification/Error-while-elaborating-batch-mode-UVM/td-p/1190182

[taichi-ishitani]

Thank you for reporting this issue.

let's wait for their feedback first, before closing it....

Yes, off cause.

[taichi-ishitani]

@aignacio , I downloaded the zip file which you attached to the forum but I cannot find a makefile for Vivado simulator. https://forums.xilinx.com/xlnx/attachments/xlnx/SIMANDVERIBD/31105/1/tvip-axi.zip Did you attached a wrong zip file?

[aignacio]

Hi @taichi-ishitani , you're right, I forgot to attach, here's the file Vivado.mk

XVLOG_ARGS  += -sv
XVLOG_ARGS  += -L uvm -relax
XVLOG_ARGS  += -log viv_compile.log
XVLOG_ARGS  += $(subst +,-d ,$(shell cat $(TEST)/test.f))
#XVLOG_ARGS += -work $(TEST)

VIV_FILE_L  = $(subst +incdir+,-i ,$(shell cat ${FILE_LISTS}))

#XELAB_ARGS += -work $(TEST)
XELAB_ARGS  += top
XELAB_ARGS  += -s $(TEST).sim
XELAB_ARGS  += -relax
XELAB_ARGS  += -L uvm -sv
XELAB_ARGS  += -timescale 1ns/1ps

CLEAN_TARGET        +=  xvlog.*
CLEAN_TARGET        +=  xelab.*
CLEAN_ALL_TARGET    +=  worklib
CLEAN_ALL_TARGET    +=  xsim.dir

.PHONY: elab_vivado compile_vivado sim_vivado

compile_vivado:
    @echo "[VIVADO] Compilation..."
    @cd $(TEST) && xvlog $(XVLOG_ARGS)  \
                           $(VIV_FILE_L)    \
                           $(SOURCE_FILES)

elab_vivado:    compile_vivado
    @echo "[VIVADO] Elaboration..."
    @cd $(TEST) && xelab $(XELAB_ARGS)

sim_vivado: elab_vivado
    @echo "[VIVADO] Simulation step"

[taichi-ishitani]

Hi @aignacio ,

The latest tvip-axi can be compiled with Vivado simulator. In addition, I've confirmed that the master agent with AXI4-Lite mode works well with this TB. https://github.com/rggen/rggen-sample-testbench

But I faced unexpected randomization errors. It's seemed that Vivado sim does not fully support constrained random number generation feature.

[taichi-ishitani]

32 is a ticket to recode changelog for Vivado support.

[aignacio]

thanks @taichi-ishitani, I'll give it another try with it!