tvip_axi_if.sv interface ports are better to be defined as logic instead of bit

@taichi-ishitani Thank you very much for your great work on this. I have just started to use your tvip-axi for AXI4-Lite master AXI4 slave memory agents. Implementation has just been completed and it works well, thanks. For further improvement, the current tvip_axi_if cannot handle Z or X states because signals are declared as bit. For example, AXI4 Lite master with tvip-axi cannot detect UVM_HAS_X status when reading registers with Z or X states. I would like you to consider this issue in the future if you have some time.

taichi-ishitani / tvip-axi

tvip_axi_if.sv interface ports are better to be defined as logic instead of bit #29