TODO - Githubissues

[ ] Complex control flow is generated in nested-loop with if/else (e.g., FFT), which leads to unmappable DFG. This is mainly because the reordered nodes make the back routing unable to close the cycle (i.e., the ordering for mapping the nodes matters). Need to look into FFT to concise the CFG and reorder the DFG nodes in a more appropriate way.
[ ] Update the cycle detection.
[x] Enable pipelinable execution for SIMD operations (e.g., Reduce).
[x] Check whether two DFG nodes are in the same cycle.
[x] Check whether the II is violated should be based on the total execution time of each cycle.
[x] Reorder the DFG (along with the longest path) at the beginning.
[x] Update to LLVM12.0 to adapt to SIMD IR.
[ ] Refine the data structure used for routing (use <cycle, opt> rather than <opt, cycle>).
[ ] Identify the register index for each operation execution, which should be explicitly shown in the generated config JSON file.
[ ] Check data dependency in arrays.

tancheng / CGRA-Mapper