Systolic array simulation

[tancheng]

Existing Systolic array CL doesn't generate correct output due to the unnecessary reset.

• [x] Fix systolic array CL model.
• [x] Figure out how the load address is correctly incremented.
  • Automatically increment on the ConstQueue.
• [x] Figure out data mem read out data.
• [x] Provide systolic array RTL model test with testbench.
• [x] Connect CGRA with 4 SRAM banks on N/W/E/S.
  • Two SRAMs look better (S/E) for matmul case.

[tancheng]

Hi @yo96, I encountered a translation issue:

/WORK_REPO/venv_latest/lib/python3.7/site-packages/pymtl3/passes/backends/verilog/translation/VerilogTranslationPass.py:134: in traverse_hierarchy
    s.translator.translate( m, m.get_metadata( c.translate_config ) )
/WORK_REPO/venv_latest/lib/python3.7/site-packages/pymtl3/passes/backends/generic/RTLIRTranslator.py:80: in translate
    raise RTLIRTranslationError( s.tr_top, msg )
E   pymtl3.passes.backends.generic.errors.RTLIRTranslationError:
E   In file /WORK_REPO/venv_latest/lib/python3.7/site-packages/pymtl3/passes/backends/verilog/translation/behavioral/VBehavioralTranslatorL1.py, Line 524, Method visit_Index:
E   Error trying to translate top component s.dut:
E   - assert not True
E    +  where True = isinstance(Const of Struct CGRAData_32_1_1_1__payload_32__predicate_1__bypass_1__delay_1, <class 'pymtl3.passes.rtlir.rtype.RTLIRType.Const'>)
E    +    where Const of Struct CGRAData_32_1_1_1__payload_32__predicate_1__bypass_1__delay_1 = <pymtl3.passes.rtlir.behavioral.BehavioralRTLIR.Index object at 0x400a7b7490>.Type
E    +    and   <class 'pymtl3.passes.rtlir.rtype.RTLIRType.Const'> = rt.Const
E     assert not isinstance( node.Type, rt.Const )

If I enable if isinstance( node.Type, rt.Const ): and remove above assertion, it would translate.

Any idea about what type of const assignment is wrong?

Reproduce:

• Checkout https://github.com/tancheng/VectorCGRA/tree/sa_sim
• $ cd cgra/translation
• pytest CGRAMemBottomRTL_Matmul_2x2_test.py -xvs --tb=short --test-verilog

[tancheng]

@yo96 figured out the culprit: s.preloadData[ i ] = preload_data[i]

Changing from s.preloadData = [ DataType( 0 ) for _ in range( data_mem_size ) ] to s.preloadData = [ Wire(DataType) for _ in range(data_mem_size) ] resolves the issue.

[tancheng]

Basically, assigning a const to another const is not expected.