Systolic array simulation

tancheng / VectorCGRA

CGRA framework with vectorization support.

BSD 3-Clause "New" or "Revised" License

19 stars 11 forks source link

Open tancheng opened 3 days ago

tancheng commented 3 days ago

Existing Systolic array CL doesn't generate correct output due to the unnecessary reset.

[x] Fix systolic array CL model.
[x] Figure out how the load address is correctly incremented.
- Automatically increment on the ConstQueue.
[x] Provide systolic array RTL model test with testbench.

tancheng commented 3 days ago

Hi @yuqisun & @yyan7223 & @cwz920716, plz review this PR. Thanks!