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tancheng / VectorCGRA

CGRA framework with vectorization support.
BSD 3-Clause "New" or "Revised" License
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Fixing inferred latches in MemUnitRTL breaks the test #5

Closed yo96 closed 1 year ago

yo96 commented 1 year ago

In fu/single/MemUnitRTL, some signals do not have a default value in the combinational block and will cause inferred latches in synthesis. However, the test breaks when I try to fix them as follow:

      s.to_mem_waddr.en     @= 0
      s.to_mem_waddr.msg    @= AddrType()
      s.to_mem_wdata.en     @= 0
      s.to_mem_wdata.msg    @= DataType()
      s.to_mem_raddr.en     @= 0
      s.to_mem_raddr.msg    @= AddrType()
      s.from_mem_rdata.rdy  @= 0