Closed jduses closed 10 months ago
Hi @jduses, for chips other than the SX1261/2, the datasheets indicates that the explicit header mode can't be used for SF<7. This makes sense because the explicit header consists in 20 bits, which need to fit within the first 8 LoRa symbols sent with CR=4/8 and low datarate optimization, which exactly gives 20 bits for SF7. To enable the explicit header for SF 5 and 6, they may have done many things (e.g. defining a different header structure, sent more symbols with CR 4/8 and LDRO, disable LDRO,...). I however didn't had the time to reverse engineer this for those chips yet.
Does this problem exists for SX1268 too?
Hi @nkaramolegos, based on the datasheets, there will be the same issue for sf5 and 6. I'll add this to the readme
Can you send me the reference? Thanks
Sure, it's described at page 36 of https://semtech.my.salesforce.com/sfc/p/E0000000JelG/a/3n000000qOUu/tpcW.qidS7dE9fxMVN_v5okCY64Xiq5OUeNNFal1a8c
Do you have any hints on how to reverse engineer these chips?
You can check this report on the reverse engineering of the rest of the physical layer to give you some hints on how you can proceed. And this nice presentation. I would be happy to accept a pull request if you add this capability!
Hi, as there is no real question pending I will close this issue for now, but don't hesitate to reopen it if needed
Hi, Can you please tell why the SF 5, 6 are not compatible with SX1261/2 chips? Is there a different whitening sequence that they use or am I missing something?