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tbarbette / fastclick

FastClick - A faster version of the Click Modular Router featuring batching, advanced multi-processing and improved Netmap and DPDK support (ANCS'15). Check the metron branch for Metron specificities (NSDI'18). PacketMill modifications (ASPLOS'21) as well as MiddleClick(ToN, 2021) are merged in main.
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About address of IIO LLC WAYS in Ice lake #392

Closed Wang4min closed 5 months ago

Wang4min commented 5 months ago

Hi, I would like to know whether there is information about IIO LLC WAYS register at 3rd Generation Intel® Xeon® Scalable Processorsa(Ice Lake-SP)?

I know that for this Intel CPU, one could only enable/disable DDIO gloably. But is there any method to tune DDIO with numbers of LLC ways?

aliireza commented 5 months ago

Hi,

I do not have access to a IceLake processor now to try it, but if there is no public information available about the registers, you can read the same register (0xC8B) and see if it contains a meaningful value (e.g., 2 set bits by default).

sudo rdmsr 0xc8b

You can find more details in the repository related to the original paper: https://github.com/aliireza/ddio-bench

Alireza

Wang4min commented 5 months ago

Hi, After entering sudo rdmsr 0xc8b, I can see a meaningful value c00 But as I type sudo wrmsr 0xc8b 0xff0 to test 1500-B packets with 4096 RX (1 core) under fastclick l3fwd (the rdmsr command output is truly ff0) , the PCIe read/write hit rates are not higher(still same). Do I miss something else for increasing the ways of IIO LLC WAYS register to achieve higher PCIe read/write hit rates?

aliireza commented 5 months ago

Your approach seems correct, but as I mentioned I have not benchmarked IceLake processors, so the uarch might have changed since my paper.

You can ask your question on Intel forum, and someone might know more about this.

Alireza