Named instance port assignment support

[ravenexp]

Both Verilog and VHDL support named instance port assignment. I understand that Hoodlum tries to stick to Rust syntax as much as possible, but HDL modules can have a very large number of ports. It is simply impossible to maintain such code with positional port assignment only.

[tcr]

@ravenexp I'm thinking the same thing, and that's now the default: https://github.com/tcr/hoodlum/blob/master/examples/rot/rot.hdl#L21

Hoodlum should borrow familiar ideas from Rust syntax, but should not at all be limited to it. Having entities mirror struct invocation though is pretty intuitive.