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tdene / adder_networks

Store of prefix tree adder HDL, diagrams, and implementation results
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Wire driven by both constant 1'b0 and the output of a ppa_buffer (brent-kung 32b adder) #2

Open tcal-x opened 2 years ago

tcal-x commented 2 years ago

Yosys complained about this (an ERROR in fact) , and it seems to be a real issue.

https://github.com/tdene/adder_networks/blob/main/adders/32bit/hdl/brent-kung.v#L460

    ppa_buffer ppa_buffer_7_7 ( .gin( {n3048} ), .pin( {n3312} ), .gout( {n3313} ), .pout( {n3654} ) );

Yosys said that tht output pout is driving a constant bit (n3654). n3654 is connected to n0 via n4047, and n0 is connected to the chain:

n4026
n3633
n3291
n436
n364
n280
n190
n97
p_lsb

p_lsb is the pout output of ppa_first_pre, which is 1'b0.

Ah, I see that the buffer output is also guaranteed to be 1'b0, since the input to this buffer is driven by another buffer that is driven by n0.

And in some ways that I run this through Yosys, it doesn't complain, and determines that all these wires are 1'b0. Perhaps it's order dependent.

tdene commented 2 years ago

The presence of n0 alone is concerning.

Those wires are all unnecessary and should be optimized out, but they should be optimized out within pptrees. Leaving them in the netlist leads to this kind of unpredictable behavior.

v1.2.0 was released recently, which should permanently eliminate any such bugs. It also eliminates all those assign statements.