failure to build due to build size too big

[fighne]

Error Arduino: 1.8.19 (Linux), Board: "Adafruit QT Py ESP32-S2, Enabled, Disabled, Disabled, Internal USB, Enabled, Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS), 240MHz (WiFi), QIO, 80MHz, 4MB (32Mb), 921600, None, Disabled"

WARNING: Category '' in library ESP Insights is not valid. Setting to 'Uncategorized' WARNING: Category '' in library ESP RainMaker is not valid. Setting to 'Uncategorized' WARNING: Category '' in library WiFiProv is not valid. Setting to 'Uncategorized' Archiving built core (caching) in: /tmp/arduino_cache_814317/core/core_esp32_esp32_adafruit_qtpy_esp32s2_CDCOnBoot_cdc,MSCOnBoot_default,DFUOnBoot_default,UploadMode_cdc,PSRAM_enabled,PartitionScheme_default,CPUFreq_240,FlashMode_qio,FlashFreq_80,FlashSize_4M,UploadSpeed_921600,DebugLevel_none,EraseFlash_none_db46359b928127ee6285ab199180f6a8.a /home/fighne/.arduino15/packages/esp32/tools/xtensa-esp32s2-elf-gcc/esp-2021r2-patch5-8.4.0/bin/../lib/gcc/xtensa-esp32s2-elf/8.4.0/../../../../xtensa-esp32s2-elf/bin/ld: ulisp-esp.ino.elf section .dram0.bss' will not fit in regiondram0_0_seg' /home/fighne/.arduino15/packages/esp32/tools/xtensa-esp32s2-elf-gcc/esp-2021r2-patch5-8.4.0/bin/../lib/gcc/xtensa-esp32s2-elf/8.4.0/../../../../xtensa-esp32s2-elf/bin/ld: region `dram0_0_seg' overflowed by 768 bytes collect2: error: ld returned 1 exit status exit status 1 Error compiling for board Adafruit QT Py ESP32-S2.

This report would have more information with "Show verbose output during compilation" option enabled in File -> Preferences.

[fighne]

so changed the Arduino Software to the latest version downloaded from the Arduino website. When verifying got the following message /home/fighne/.arduino15/packages/esp32/tools/xtensa-esp32s2-elf-gcc/esp-2021r2-patch5-8.4.0/bin/../lib/gcc/xtensa-esp32s2-elf/8.4.0/../../../../xtensa-esp32s2-elf/bin/ld: /tmp/arduino/sketches/DBEE89D8A01FE8CDA34704BA42B65863/ulisp-esp.ino.elf section .dram0.bss' will not fit in regiondram0_0_seg' /home/fighne/.arduino15/packages/esp32/tools/xtensa-esp32s2-elf-gcc/esp-2021r2-patch5-8.4.0/bin/../lib/gcc/xtensa-esp32s2-elf/8.4.0/../../../../xtensa-esp32s2-elf/bin/ld: region `dram0_0_seg' overflowed by 2016 bytes collect2: error: ld returned 1 exit status

exit status 1

Compilation error: exit status 1

[technoblogy]

The latest ESP32 core seems to use more RAM, so I think the solution is to reduce the RAM allocated to uLisp by reducing the WORKSPACESIZE setting to, for example:

#elif defined(ARDUINO_ADAFRUIT_QTPY_ESP32S2)
  #define WORKSPACESIZE (8000-SDSIZE)            /* Cells (8*bytes) */

If that works you can get the maximum workspace by increasing it in steps until it fails.

[fighne]

Thank you your first suggestion worked perfectly, even tried 8040 and that failed.

[technoblogy]

Great - glad it worked!