Infrastructure to enable deployment of ML models to low-power resource-constrained embedded targets (including microcontrollers and digital signal processors).
The CI sync from the upstream TF has been failing for the last month due to the relocation of certain TFLite files. In particular, some schema files were relocated to tensorflow/compiler/mlir/lite subfolder. This PR mirrors the migration and adds a few redirection headers to ensure source compatibility for now.
This PR also includes a TF sync as well to get us caught up again. While that could have been done separately, this is done together to ensure everything continues to build with the relocations.
The CI sync from the upstream TF has been failing for the last month due to the relocation of certain TFLite files. In particular, some schema files were relocated to tensorflow/compiler/mlir/lite subfolder. This PR mirrors the migration and adds a few redirection headers to ensure source compatibility for now.
This PR also includes a TF sync as well to get us caught up again. While that could have been done separately, this is done together to ensure everything continues to build with the relocations.
BUG=b/351824449