This change adds support for the device dram memory space in metal
backend. This required a few bits of refactoring including:
DeviceAttr splits out worker grid from L1 map, they now respectively
map the physical compute cores and the physical L1 memory map.
DeviceAttr gets a new map, dramMap, which maps a linear tensor
coordinate to a physical dram address.
Change projectOnto to take an arbitrary affine map instead of a grid
attr. This let's us pass in unique affine map for L1 or DRAM or Eth
(in the future) to the same interface.
PhysicalCoreCoordMapping can now take an L1 grid or a DRAM grid.
Giving explicit enum index names for the DeviceAttr affine map
results.
Noc datamovement program can now be generated as reads or writes,
necessary for writing to DRAM since dram cores do not have risc.
This change adds support for the device dram memory space in metal backend. This required a few bits of refactoring including:
DeviceAttrsplits out worker grid from L1 map, they now respectively map the physical compute cores and the physical L1 memory map.DeviceAttrgets a new map,dramMap, which maps a linear tensor coordinate to a physical dram address.projectOntoto take an arbitrary affine map instead of a grid attr. This let's us pass in unique affine map for L1 or DRAM or Eth (in the future) to the same interface.PhysicalCoreCoordMappingcan now take an L1 grid or a DRAM grid.Closes #359