We set the high bit of $2115 to 0, which instructs the PPU to increment the VRAM word address after writing the low data byte. However, the DMA transfer writes low bytes first, then high bytes. This means the high byte of the first word of a transfer was being skipped, leading to an occasional glitchy tile. Setting the mode bit to 1 instead fixes the issue.
We set the high bit of
$2115
to 0, which instructs the PPU to increment the VRAM word address after writing the low data byte. However, the DMA transfer writes low bytes first, then high bytes. This means the high byte of the first word of a transfer was being skipped, leading to an occasional glitchy tile. Setting the mode bit to 1 instead fixes the issue.