The error reporting feature added in #7 signals errors on the bus interface if a request to a non-existent address is made. This PR extends the error reporting feature to also return errors when the request type does not match the access rights of the register, i.e., if you do a write request to a read-only register, or a read request to a write-only register.
The feature is rather straight forward an implemented in 42021048f88e03b8564f754bd44b13db64ffa671. Unfortunately, the way the APB interface is implemented, there were some additional modification needed to make it work: Following the standard, an APB request takes two cycles (or phases): During the first cycle, the request is initialized (setup phase), and during the second cycle the request is treated (access phase). The internal bus request as used by cheby is generated based on the first cycle. The way the access error feature is implemented, such an error is returned immediately based on the internal bus request. Hence, in case of the APB request, the error is signaled during the first (instead of the second) request. To make it work, an additional signal was added to the internal bus, which consists of a delayed version of the request signals. Please let me know if that works for you.
The error reporting feature added in #7 signals errors on the bus interface if a request to a non-existent address is made. This PR extends the error reporting feature to also return errors when the request type does not match the access rights of the register, i.e., if you do a write request to a read-only register, or a read request to a write-only register.
The feature is rather straight forward an implemented in 42021048f88e03b8564f754bd44b13db64ffa671. Unfortunately, the way the APB interface is implemented, there were some additional modification needed to make it work: Following the standard, an APB request takes two cycles (or phases): During the first cycle, the request is initialized (setup phase), and during the second cycle the request is treated (access phase). The internal bus request as used by cheby is generated based on the first cycle. The way the access error feature is implemented, such an error is returned immediately based on the internal bus request. Hence, in case of the APB request, the error is signaled during the first (instead of the second) request. To make it work, an additional signal was added to the internal bus, which consists of a delayed version of the request signals. Please let me know if that works for you.