Pipeline reset value for multi-bit signals

[lorenzschmid]

When enabling a pipeline, cheby instantiates an additional synchronous process, which

1. resets the pipelined signal, and
2. assigns the actual value to the pipelined signal upon a rising clock edge.

Unfortunately, cheby implements step 1 only for signals with a size of 1 bit. Signals with a size greater than one bit are only added in step 2. I.e., in the following example rd_adr_d0 has no reset assignment while the single-bit signal rd_req_d0 does:

  -- pipelining for rd-in
  process (pclk) begin
    if rising_edge(pclk) then
      if presetn = '0' then
        rd_req_d0 <= '0';
      else
        rd_req_d0 <= rd_req;
        rd_adr_d0 <= rd_addr;
      end if;
    end if;
  end process;

This PR fixes this behavior in c0d21f8bd5835e312eb0a917e058cc42eee21a14 by adding a zero constant value as reset assignment for multip-bit signals.

[tgingold-cern]

Thanks!