Run RTL elaboration (using ghdl, verilator) during CI tests
Use argparse to set flags in tests.py
Add necessary SV wishbone package and dpssram
Resolve issues that broke RTL elaboration:
AXI4 Lite: Fix rdata assignment width (SV only)
GenMemory: Make sure sel_int name is unique (VHDL and SV)
WBBus: Fix address generation with zero-width parts, e.g. sub_o.adr <= ((29 downto 0 => '0') & wb_adr_i(1 downto 2)) & (1 downto 0 => '0'); (I guess this is legal in VHDL (?), but not in SV)
SV: Fix interface generation (remove extra comma)
SV: Use ~instead ! as not operator (works for both scalars and bit-vectors).
I've split out the changes to the golden test files into separate commits to help with the review.
Hi @tgingold-cern
I started with the idea of running elaboration tests on the generated RTL files and I also thought it might be a good idea to also run the generation tests for SV. I added elaboration tests for VHDL using ghdl and for SV using verilator, which worked quite nicely locally. I also discovered a few bugs in the SV generation and one VHDL issue that I fixed.
However, when I set up the Github CI job, I noticed that there was a problem with the packaged version of verilator (v4). It didn't like the top-level interface ports and resulted in errors. So instead I used verilator within an apptainer/singularity container (I didn't find a nice way to make it work with docker). This works, but it's somewhat ugly and quite slow... Let me know if you'd prefer to merge it without the apptainer verilator stuff.
tgingold-cern
commented
8 months ago
Changes:
sel_intname is unique (VHDL and SV)sub_o.adr <= ((29 downto 0 => '0') & wb_adr_i(1 downto 2)) & (1 downto 0 => '0');(I guess this is legal in VHDL (?), but not in SV)~instead!as not operator (works for both scalars and bit-vectors).Example pipeline: https://github.com/stefanlippuner/cheby/actions/runs/6761939542/job/18377329305
I've split out the changes to the golden test files into separate commits to help with the review.
Hi @tgingold-cern
I started with the idea of running elaboration tests on the generated RTL files and I also thought it might be a good idea to also run the generation tests for SV. I added elaboration tests for VHDL using ghdl and for SV using verilator, which worked quite nicely locally. I also discovered a few bugs in the SV generation and one VHDL issue that I fixed.
However, when I set up the Github CI job, I noticed that there was a problem with the packaged version of verilator (v4). It didn't like the top-level interface ports and resulted in errors. So instead I used verilator within an apptainer/singularity container (I didn't find a nice way to make it work with docker). This works, but it's somewhat ugly and quite slow... Let me know if you'd prefer to merge it without the apptainer verilator stuff.
Cheers Stefan