Fix trailing semicolon for VHDL entities without ports

[lorenzschmid]

If all registers in a memory map are of type no-port, the entity does not have any ports besides the interface ports. Since in VHDL, the interface ports are always generated with a ;, the entity then has a trailing semicolon:

    ...
    prdata               : out   std_logic_vector(31 downto 0);
    pslverr              : out   std_logic;
  );
end no_port;

instead of (see after std_logic):

    ...
    prdata               : out   std_logic_vector(31 downto 0);
    pslverr              : out   std_logic
  );
end no_port;

This fix introduces an IO buffer in Python to which all strings are written first. Then, the very last semicolon gets removed before the buffer is written into the output file. Also, the no_port testcase is updated to verify this new behavior.