Verilog - Use appropriate assignment operator, split tests between Verilog and SV

[stefanlippuner]

Follow-up from https://github.com/tgingold-cern/cheby/pull/31

Given that the intent is to support both SystemVerilog and Verilog (at least partially), I think we should test the generation of both in CI. This PR implements that and fixes one issue that was detected using the new elboration test.

Functional changes

• Use blocking '=' for comb, non-blocking '<=' for sync (sequential) logic.
  • This is one of the 'Golden Rules of Verilog', see C. E. Cummings, "Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!" (http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf). Not following this rule can lead to weird behaviour in Simulation. Using <= in an always_comb also results in a Verilator warning (https://verilator.org/guide/latest/warnings.html#cmdoption-arg-COMBDLY).

Testing changes

• Generate and elaborate both SV and Verilog RTL files separately.
• Update the golden test files.