Couple of remarks from a fresh start

[SebastianHambura]

Hi,

First, thanks a lot for this tools, I've tried a couple of things and it look like it will greatly help me !

I have a couple of remarks :

1. when installing on a fresh Python venv (on windows), I had to manually install setuptools even after pip install -r .\requirements.rxt

2. The documentation on how to use the RAMs is a bit sparse. In my generated verilog code, there is an instance of cheby_dpssram. Is it the module that can be found at https://github.com/tgingold-cern/cheby/blob/master/testfiles/tb/dpssram.sv ?

3. I've tried using x-map-info/memmamp-version, but I get parse error: unhandled 'memmamp-version' in x-map-info. What's the correct syntax ? My test file looked like:

   memory-map:
   bus: axi4-lite-32
   name: bram_module
   word-endian: little
   x-map-info:
   memmamp-version: 1.2.3
   ident: 0x11
   children:
   - reg:
       name: enable
       description: |
         Enable or disable the whole module
       type: unsigned
       width: 32
       access: rw
   - memory:
       name: ram_rol
       memsize: 16
       children:
         - reg:
             name: value
             access: rw
             width: 32

4. Is there an easy was to add a custom extension ? We're writing the software part in Rust, so I'm wondering if it's possible/worth it to convert the .yaml directly into a rust mod through cheby.

[tgingold-cern]

1. no idea for windows. If you know how to fix, please create a PR!
2. yes, for internal memories, you have to provide the implementation. There are a few examples within Cheby repo. Probably, you'd better to use external memories.
3. I'ts memmap-version
4. There is a simple plugin mechanism, but it is probably too simple. For generating rust, you can probably starts from how constant files are generated. Again, a PR is welcome (as well as some tests !)

[augustofg]

@tgingold-cern It is possible to specify an external memory interface using cheby? I couldn't find how to do this reading the documentation.

[tgingold-cern]

Yes, just use interface.

[augustofg]

Thanks @tgingold-cern! Looking at the cheby source code I've figured that it is possible to set the interface attribute to sram which does exactly what I want:

memory-map:
  bus: wb-32-be
  name: wb_ram
  description: Wishbone RAM interface
  x-hdl:
    busgroup: true
  children:
    - memory:
        name: ram
        memsize: 32768
        interface: sram
        children:
          - reg:
              name: data
              access: rw
              width: 32