Vivado IPI compatibility

[iljabek]

if using the cheby-generated AXI4-Lite interface in Vivado block design without a wrapper following issues arise:

• the naming of the interface does not follow usual scheme of [MS]_AXI_NAME, instead slave is produced
• even if enabling the x-attributes, the reset pin does not quite follow auto-discovery naming scheme because of underscore in areset_n and is not associated with the aclk clock pin
• the aclk pin is not automatically associated with the port in properties

minimal yaml example:

memory-map:
  name: info
  bus: axi4-lite-32
  x-hdl:
    bus-attribute: Xilinx

Current IP in BD + post-autoconnect:

minimal "valid" IP in BD + post-autoconnect:

• this can be achieved via x-attributes
• desirable is also to customize the names:

[iljabek]

@tgingold-cern I have to look into the failing test, but is this https://github.com/iljabek/cheby/commit/095f911874880a79eeb2a5248dca565f75e972bb going in good general direction? would you prefer to split the minimal and customization commits?

[tgingold-cern]

Yes, I think this is OK. I would use 'clock-name' and 'reset-name' instead of 'bus-clock-name' and 'bus-reset-name'

Not sure why you need 'use-bus-name-in-ports'. There is a 'reg-prefix' which might do what you'd like.

[iljabek]

There is a 'reg-prefix' which might do what you'd like

can the bus name consist only out of reg-prefix, i.e. name be empty?

[tgingold-cern]

I think that reg-prefix has no influence on bus name, only on ports (and internal names).